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Race Timing Jobs (NOW HIRING)

Vibra Travels

INDYCAR Race Engineer

Indianapolis, IN

... timing and logged data to provide to the driver. Liaise with the race team over the specification ... of the car - it's intended run plan and preparation of test parts and test points. During the event ...

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How much do race timing jobs pay per year?

As of Jul 12, 2026, the average yearly pay for race timing in the United States is $58,981.00, according to ZipRecruiter salary data. Most workers in this role earn between $41,000.00 and $77,000.00 per year, depending on experience, location, and employer.

What are the typical responsibilities of someone working in Race Timing at sporting events?

Professionals in Race Timing are responsible for setting up timing equipment at event sites, ensuring all systems are functioning correctly, and coordinating with event organizers before and during races. On event day, they monitor timing systems, process participant data in real time, and troubleshoot any technical issues that arise. After the race, they verify results for accuracy and may assist in reporting and distributing official times. This role often involves working early mornings, weekends, and occasional travel, and requires excellent teamwork with race directors, volunteers, and technical staff.

What is a Race Timing job?

A Race Timing job involves managing the timing and results of races, such as marathons, triathlons, and cycling events. Race timers set up and operate timing equipment, ensure accurate participant tracking, and process race results. They may use RFID chips, manual timing systems, or other technologies to record finish times. This role requires attention to detail, technical skills, and the ability to work in fast-paced environments. Race timers often collaborate with event organizers to ensure smooth race operations and accurate reporting.

What are the key skills and qualifications needed to thrive in the Race Timing position, and why are they important?

To thrive in Race Timing, candidates should have strong organizational skills, attention to detail, and a basic understanding of event management or sports administration. Familiarity with race timing software and hardware, such as RFID chip systems, finish line cameras, and data management platforms, is highly recommended. Effective communication, problem-solving skills, and the ability to remain calm under pressure are essential soft skills in this role. These attributes help ensure accurate results, smooth event operations, and a positive experience for both participants and organizers.

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Race Timing jobs near you
SOC Physical Design Static Timing Analysis Engineer

SOC Physical Design Static Timing Analysis Engineer

Intel

Phoenix, AZ

$164K - $311K/yr

Full-time

Medical, Retirement, PTO

Re-posted 14 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 146 frontline employees who took The Breakroom Quiz

11th of 142 rated electronics manufacturers

Job description

Job Details:Job Description: 

As a Physical Design Timing Engineer, you will play a pivotal role in shaping the performance, power efficiency, and functionality of Intel's cutting-edge System-on-Chip (SoC) designs. Your expertise will directly impact product quality, enabling groundbreaking advancements in technology that drive computing innovation. Collaborating across multiple teams, you will contribute to the creation and optimization of high-performance, low-power solutions while developing methodologies that enhance efficiency and operational excellence. This is an exciting opportunity to work on complex designs that have a global impact, delivering solutions that power today's world and inspire tomorrow's possibilities.

Key Responsibilities:

  • Perform SOC level timing analysis and optimization, ensuring designs meet functional and performance requirements.
  • Generate and verify timing constraints while addressing timing violations at the chip or block level for SoCs.
  • Conduct timing rollups and develop optimized clock networks for functionality, performance, and power efficiency.
  • Define methodologies to produce high-quality timing models and enable efficient physical design execution.
  • Establish the appropriate process, voltage, and temperature (PVT) conditions for timing analysis, aligning with product plans, and binning strategies.
  • Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning.
  • Collaborate with architecture, clocking design, DFT and logic design teams to develop flows for chip integration and validate clock network performance guidelines.
  • Contribute to the development of tools, flows, and methodologies that enhance SoC physical design and timing processes.
Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Qualifications

  • Bachelor's degree with 8 +years or master's degree with 6+ years or PhD with 4+ years in Electrical Engineering or Computer Engineering or Computer Science or a related field.
  • 7+ years technical proficiency in SOC level static timing analysis, clock network design, and timing closure methodologies.
  • 3+ years of experience with the following skills:
  • Strong expertise in timing constraint adaptation, physical design knowledge, and optimization techniques.
  • Proficiency with industry-standard tools for timing analysis, extraction, and physical design.
  • Familiarity with TCL scripting and timing budgeting processes.

Preferred Skills/Experience:

  • Demonstrated ability to collaborate across diverse teams and drive innovative solutions for SoC designs.
  • Experience with SoC clocking methodologies, disciplined execution, and problem-solving in digital design.
  • Knowledge of tools, flows, and methodologies for high-performance physical design.
  • Strong communication skills and ability to articulate technical concepts effectively.
  • DFT architecture knowledge is a strong plus
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Arizona, PhoenixAdditional Locations:US, California, Santa ClaraBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

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Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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