... Engineering, or a related discipline. Technical Experience: * Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between ...
... Engineering, or a related discipline. Technical Experience: * Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between ...
... Engineering, or a related discipline. Technical Experience: * Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between ...
... Engineering, or a related discipline. Technical Experience: * Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between ...
... Engineering, or a related discipline. Technical Experience: * Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between ...
... Engineering, or a related discipline. Technical Experience: * Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between ...
Staff Design Engineer, HBM
Richardson, TX · On-site
As an HBM Memory Design Engineer - Sustaining (Staff) , you will work closely with cross-functional teams including Design Engineering (DE), Product Engineering (PE), Process Integration, Packaging ...
Staff Design Engineer, HBM
Richardson, TX · On-site
As an HBM Memory Design Engineer - Sustaining (Staff) , you will work closely with cross-functional teams including Design Engineering (DE), Product Engineering (PE), Process Integration, Packaging ...
... Engineering, or a related discipline. Technical Experience: * Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between ...
... Engineering, or a related discipline. Technical Experience: * Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between ...
Non-Volatile Memory Design Architecture Lead
San Jose, CA · On-site
$184K - $322K/yr
As a Design Architecture Lead in Non-Volatile-Engineering NAND Flash design team at Micron ... Innovate and architect innovative memory/storage solution for high performance and energy efficient ...
Non-Volatile Memory Design Architecture Lead
San Jose, CA · On-site
$184K - $322K/yr
As a Design Architecture Lead in Non-Volatile-Engineering NAND Flash design team at Micron ... Innovate and architect innovative memory/storage solution for high performance and energy efficient ...
Staff Design Engineer, HBM
Richardson, TX · On-site
As an HBM Memory Design Engineer - Sustaining (Staff) , you will work closely with cross-functional teams including Design Engineering (DE), Product Engineering (PE), Process Integration, Packaging ...
Staff Design Engineer, HBM
Richardson, TX · On-site
As an HBM Memory Design Engineer - Sustaining (Staff) , you will work closely with cross-functional teams including Design Engineering (DE), Product Engineering (PE), Process Integration, Packaging ...
Experienced Memory Device/Bitcell Engineer
$149K - $210K/yr
Experienced Memory Device/Bitcell Engineer Salary: $149,465-$210,000/year Hours: Monday - Friday, 8 ... Perform specialized design and develop devices, understands the process integration that leads to ...
Experienced Memory Device/Bitcell Engineer
$149K - $210K/yr
Experienced Memory Device/Bitcell Engineer Salary: $149,465-$210,000/year Hours: Monday - Friday, 8 ... Perform specialized design and develop devices, understands the process integration that leads to ...
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... Our Design Engineering organization delivers groundbreaking silicon-to-systems solutions by ...
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... Our Design Engineering organization delivers groundbreaking silicon-to-systems solutions by ...
Experienced Memory Device/Bitcell Engineer
New York, NY · On-site
$149K - $210K/yr
Experienced Memory Device/Bitcell Engineer Salary: $149,465-$210,000/year Hours: Monday - Friday, 8 ... Perform specialized design and develop devices, understands the process integration that leads to ...
Experienced Memory Device/Bitcell Engineer
New York, NY · On-site
$149K - $210K/yr
Experienced Memory Device/Bitcell Engineer Salary: $149,465-$210,000/year Hours: Monday - Friday, 8 ... Perform specialized design and develop devices, understands the process integration that leads to ...
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... Our Design Engineering organization delivers groundbreaking silicontosystems solutions by ...
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... Our Design Engineering organization delivers groundbreaking silicontosystems solutions by ...
Senior Memory System Engineer
Santa Clara, CA · On-site
$122K - $167K/yr
Experience in the design, bring-up and validation for memory failure analysis * Experience with ... class engineering teams are rapidly growing. If you're creative and autonomous, we want to hear ...
Senior Memory System Engineer
Santa Clara, CA · On-site
$122K - $167K/yr
Experience in the design, bring-up and validation for memory failure analysis * Experience with ... class engineering teams are rapidly growing. If you're creative and autonomous, we want to hear ...
Memory Control Design Engineer
San Diego, CA · On-site
$115K - $173K/yr
QCT Memory Controller Design Team is looking for ASIC Design Engineers for the next generation high speed DDR Controllers. The front end of the DDR controller interfaces to the rest of the system ...
Memory Control Design Engineer
San Diego, CA · On-site
$115K - $173K/yr
QCT Memory Controller Design Team is looking for ASIC Design Engineers for the next generation high speed DDR Controllers. The front end of the DDR controller interfaces to the rest of the system ...
As an HBM Memory Design Engineer within the HBM Architecture Team, you will design, simulate, and optimize digital and analog DRAM circuits for nextgeneration highbandwidth memory products. You will ...
As an HBM Memory Design Engineer within the HBM Architecture Team, you will design, simulate, and optimize digital and analog DRAM circuits for nextgeneration highbandwidth memory products. You will ...
Senior Memory System Engineer
Santa Clara, CA · Hybrid
$122K - $167K/yr
Experience in the design, bring-up and validation for memory failure analysis * Experience with ... class engineering teams are rapidly growing. If you're creative and autonomous, we want to hear ...
Senior Memory System Engineer
Santa Clara, CA · Hybrid
$122K - $167K/yr
Experience in the design, bring-up and validation for memory failure analysis * Experience with ... class engineering teams are rapidly growing. If you're creative and autonomous, we want to hear ...
New College Grad - Design Engineer, HBM DFT
Richardson, TX · On-site
$90K - $124K/yr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As part of the Design for Test (DFT) Engineering team, this role contributes to enabling ...
New College Grad - Design Engineer, HBM DFT
Richardson, TX · On-site
$90K - $124K/yr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As part of the Design for Test (DFT) Engineering team, this role contributes to enabling ...
As an HBM Memory Design Engineer within the HBM Architecture Team, you will design, simulate, and optimize digital and analog DRAM circuits for next-generation high-bandwidth memory products. You ...
As an HBM Memory Design Engineer within the HBM Architecture Team, you will design, simulate, and optimize digital and analog DRAM circuits for next-generation high-bandwidth memory products. You ...
New College Grad - Design Engineer, HBM DFT
Richardson, TX · On-site
$90K - $124K/yr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As part of the Design for Test (DFT) Engineering team, this role contributes to enabling ...
New College Grad - Design Engineer, HBM DFT
Richardson, TX · On-site
$90K - $124K/yr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As part of the Design for Test (DFT) Engineering team, this role contributes to enabling ...
Design Engineer
San Jose, CA · On-site
Drive OVM/UVM design verification and support FPGA engineers for early prototyping. * Execute RTL ... memory.
Quick apply
Design Engineer
San Jose, CA · On-site
Drive OVM/UVM design verification and support FPGA engineers for early prototyping. * Execute RTL ... memory.
Analog Design Engineer
Rancho Cordova, CA · On-site
$121K - $194K/yr
Solidigm will continue to lead the world in innovating new Memory technologies with aspirations to ... Design and development of analog and mixed-signal circuits for 3D NAND Flash memory , supporting ...
Analog Design Engineer
Rancho Cordova, CA · On-site
$121K - $194K/yr
Solidigm will continue to lead the world in innovating new Memory technologies with aspirations to ... Design and development of analog and mixed-signal circuits for 3D NAND Flash memory , supporting ...
Memory Design Engineer information
See salary details
$96K is the 25th percentile. Wages below this are outliers.
$80.5K - $99.6K
31% of jobs
$99.6K - $118.7K
5% of jobs
The median wage is $132.5K / yr.
$118.7K - $137.8K
19% of jobs
$152.5K is the 75th percentile. Wages above this are outliers.
$137.8K - $156.9K
26% of jobs
$156.9K - $176K
13% of jobs
$176K - $195K
4% of jobs
$195K - $214.1K
0% of jobs
$214.1K - $233.2K
0% of jobs
$233.2K - $252.3K
0% of jobs
$252.3K - $271.4K
1% of jobs
$271.4K - $290.5K
1% of jobs
$80.5K
$141.4K
$290.5K
How much do memory design engineer jobs pay per year?
What are the primary challenges faced by Memory Design Engineers on a daily basis?
Memory Design Engineers often encounter challenges such as optimizing memory circuits for speed, power efficiency, and area while ensuring manufacturability and meeting reliability standards. Balancing these conflicting requirements requires strong analytical skills and close collaboration with verification, process, and layout teams. The role also involves troubleshooting design issues, staying updated with evolving semiconductor technologies, and ensuring timely project delivery. Overcoming these challenges fosters professional development and helps engineers build a solid track record in advanced technology nodes.
What are the key skills and qualifications needed to thrive in the Memory Design Engineer position, and why are they important?
A Memory Design Engineer requires a strong background in electrical engineering, semiconductor physics, and digital/analog circuit design, typically supported by a relevant bachelor's or master's degree. Expertise with EDA tools like Cadence, Synopsys, or Mentor Graphics, and familiarity with scripting languages and memory characterization tools is essential. Strong problem-solving skills, attention to detail, and effective communication are important soft skills in this role. These competencies are crucial to ensure reliable, high-performance memory designs that meet rigorous industry standards and enable smooth collaboration within multidisciplinary engineering teams.
What engineers make $500,000?
What does a memory design engineer do?
What is the salary of memory layout design engineer?
What is a Memory Design Engineer job?
A Memory Design Engineer is responsible for designing, developing, and optimizing memory circuits such as SRAM, DRAM, or flash memory. They work on transistor-level design, layout, simulation, and verification to ensure performance, power efficiency, and reliability. Engineers collaborate with process, verification, and product teams to meet design specifications and manufacturing constraints. Their role is critical in advancing memory technology for applications in consumer electronics, computing, and enterprise solutions.
What jobs can DT get you?
Intel rating
8.7
Based on 144 frontline employees who took The Breakroom Quiz
10th of 139 rated electronics manufacturers
Job description
The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.
The Advanced Design (AD) team is part of Intel's larger Design Technology Platform (DTP) Organization and is focused on pathfinding and development of advanced memory technology. These circuits enable best-in-class memory collateral, IP and innovative product design across all generations of Intel process technology. At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable Intel's internal and external customers to get to the market faster with products that include high-performance, high-density, low-power memory at the leading edge of the technology curve and implemented in Intel's advanced CMOS process technologies.
You will be partnering with and leveraging domain experts across various areas of technology development, EDA vendors and product design teams to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on Intel advanced CMOS process technologies. In this position your responsibilities will include, but may not be limited to:
- Memory pathfinding activities and power, performance and area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement.
- Memory bit-cell and complex periphery IC layout and automation.
- Memory array/IP design, memory circuit innovation, test-chip design.
- Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp.
You must possess the minimum qualifications listed below to interview for this position. Preferred qualifications are not required but may work to your advantage during the interview process.
Minimum Qualifications:
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline, including 4+ years of professional experience gained through either internships or full-time employment Or a PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline.
Technical Experience:
- Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM.
- Design trade-offs between power, performance, and area (PPA).
- Custom digital circuit design, simulation, layout design, and verification.
- Knowledge of EDA tools used for custom digital and memory circuit design.
Preferred Qualifications:
- PhD with 1-2 years of professional experience gained through either internships or full-time employment.
- Design technology co-optimization (DTCO).
- Post-Si validation experience.
- Knowledge of the CMOS ASIC design flow.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968