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Part Time Memory Design Engineer Jobs (NOW HIRING)

Saratech

Design Engineer

Mission Viejo, CA · On-site

$30 - $50/hr

Saratech is seeking a part-time Design Engineer. You will assist the Engineering Services/Design team with various support duties such as CAD modeling, part model check reviews, industry standard ...

Saratech

Design Engineer

Mission Viejo, CA · Remote

$30 - $50/hr

Saratech is seeking a part-time Design Engineer. You will assist the Engineering Services/Design team with various support duties such as CAD modeling, part model check reviews, industry standard ...

Saratech, Inc.

Design Engineer

Mission Viejo, CA

$30 - $50/hr

Saratech is seeking a part-time Design Engineer. You will assist the Engineering Services/Design team with various support duties such as CAD modeling, part model check reviews, industry standard ...

Harley-Davidson

Senior Design Engineer

Wauwatosa, WI

Senior Design Engineer Job Function: Engineering Location: PDC Workplace Category: Onsite Company ... Harley-Davidson Motor Company Full or Part-Time: Full Time Shift: SHIFT1 In 1903, out of a small ...

Harley-Davidson

Senior Design Engineer

Wauwatosa, WI · On-site

Senior Design Engineer Job Function: Engineering Location: PDC Workplace Category: Onsite Company ... Harley-Davidson Motor Company Full or Part-Time: Full Time Shift: SHIFT1 In 1903, out of a small ...

Arcadis

Roadway Design Engineer

Detroit, MI · On-site

$90K - $110K/yr

As the Lead Roadway Design Engineer , you will play a pivotal role in overseeing and managing ... Arcadis offers benefits for full time and part time positions. These benefits include medical ...

W3Global Inc.

Electrical Design Engineer

Southlake, TX

$75K - $85K/yr

About the Role Our client is seeking an experienced Electrical Design Engineer to join a dynamic ... part-time work. A degree is not required for this position. Every project is custom-designed ...

Oregonstate

Mechanical Design Engineer

Corvallis, OR

$78K - $106K/yr

All job offers are contingent upon Human Resources final approval This recruitment will be used to fill one part-time (a maximum of 24 hours per week) Mechanical Design Engineer position for the ...

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Part Time Memory Design Engineer information

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$80.5K

$141.4K

$290.5K

How much do part time memory design engineer jobs pay per year?

As of Aug 1, 2026, the average yearly pay for part time memory design engineer in the United States is $141,351.00, according to ZipRecruiter salary data. Most workers in this role earn between $95,000.00 and $158,000.00 per year, depending on experience, location, and employer.
What are the most commonly searched types of Memory Design Engineer jobs? The most popular types of Memory Design Engineer jobs are:
Part Time Memory Design Engineer jobs near you
Infographic showing various Part Time Memory Design Engineer job openings in the United States as of July 2026, with employment types broken down into 88% Full Time, 9% Part Time, and 3% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $141,351 per year, or $68 per hour.

Sr. / Staff ASIC Digital Design Engineer

SK hynix memory solutions America Inc.

San Jose, CA • On-site

$110K - $170K/yr

Full-time, Part-time

Medical, Dental, Vision, Life, Retirement

Posted 16 days ago

Job description

About the Company:
At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.
We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change - we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.
Position Overview
We are looking for a highly motivated ASIC Digital Design engineer with expertise in DFT, Synthesis, Power, and Timing analysis to support our hardware engineering team.
As a member of ASIC implementation team, you are expected to drive automated flows to streamline sign-off for multiple teams, and ensure high quality deliveries to achieve tapeout milestones.
Key Responsibilities
  • Extensive experience with Synopsys tool suites, and Siemens Tessent tool suite.
  • Responsible for top-level DFT planning and integration.
  • Managing the ATPG (Automatic Test Pattern Generation) and ATE (Automated Test Equipment) interface, including ATE bring-up and failure analysis.
  • Driving test time reduction strategies.
  • Leading Synthesis , Formality, Timing checks, provide guidance, interface with RTL design team for quality RTL delivery.
  • Full chip and Block constraints development & STA; Working independently with the PNR & RTL design team on Physical implementation & Power-intent requirements.
  • Power & IR analysis; implementing DFT across multi-power domain designs.
  • Troubleshooting Synthesis / Timing / DFT / Power related issues, continuously driving flow improvements.
  • Help maintain scripts, documentation, IP DK, and SoC signoff checklists.

Required Qualifications
  • Demonstrate expertise in multiple Tapeouts, Extensive experience in frontend tools such as PT, DC, VCLP, Formality, LEC, PrimeClosure, PrimePower, VCS, VC-spyglass-dft, Tetramax, Tessent, etc.
  • Low-Power Design flow with UPF.
  • Familiarity with UNIX/Linux environments, tcl/perl/python/shell scripting, AI-assisted flow experience is a plus.
  • Strong attention to detail and ability to follow structured workflows.
  • Bachelors in Engineering and 8+ years of related experience, or Masters degree in Engineering and 6+ years of related experience.

Preferred Qualifications
  • Direct experience taping out designs in advanced semiconductor technology nodes (e.g., 7nm, 5nm, or below).
  • Familiarity with voltage drop analysis.
  • Experience with ATE bring-up, failure analysis and yield improvement.
  • Experience with CDC/RDC/Lint checks.
  • Experience with floorplan / timing-driven placement / clock-tree synthesis / Xtalk analysis.

COMPENSATION: $110,000 - $170,000
REGARDING COMPENSATION:
SK hynix memory solutions America Inc. offers you the opportunity to apply your skills to exciting projects while working with innovative teams. Our compensation package is complimented by a generous benefits package including medical, dental, vision, life insurance and a company 401(k) match, as well as cafeteria, onsite gym and much more. If you are motivated by technical challenges, we offer a collaborative work environment that encourages career growth.
The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness.

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