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Manager Memory Design Engineer Jobs (NOW HIRING)

Resource Point LLC

Memory Design Engineer

Troy, MI · On-site

Memory Design Engineer Location: Ontario, Canada Duration: 6+ Months with possible extension Qualification Required: * Typically requires minimum of 2 to 5 years of experience in Memory Design with ...

Arm Limited

Memory Design Engineer

Austin, TX · On-site

$130K - $176K/yr

Contribute in all parts of the memory development flow, starting at design specification, circuit ... Master's in Electrical Engineering, Computer Engineering, or other relevant technical fields with ...

ARM

Memory Design Engineer

Austin, TX · Hybrid

$130K - $176K/yr

Contribute in all parts of the memory development flow, starting at design specification, circuit ... Master's in Electrical Engineering, Computer Engineering, or other relevant technical fields with ...

ARM

Memory Design Engineer

Austin, TX · On-site

$130K - $176K/yr

Contribute in all parts of the memory development flow, starting at design specification, circuit ... Master's in Electrical Engineering, Computer Engineering, or other relevant technical fields with ...

Intel

CPU Circuit Memory Design Engineer

Austin, TX · On-site

About the Role Intel's CPU Circuit Technology team is seeking a highly motivated CPU Memory Design Engineer to help develop the next generation of high-performance, power-efficient processors. In ...

Micron

Memory Design Engineer, HBM

Richardson, TX

As a Design Engineer at Micron Technology, Inc., you will be responsible for designing and analyzing digital and analog circuits used in the development of memory products. We are engaged in ...

Micron Technology, Inc

DRAM Design Engineer

Boise, ID · On-site

Job Summary As a Design Engineer at Micron Technology, Inc., you will be responsible for designing ... You will provide high‑quality, efficient, and reliable memory solutions that optimize ...

Micron

Senior Memory Design Engineer, HBM

Richardson, TX · On-site

... memory products. This role collaborates globally across design, verification, product engineering ... Manage layout and develop resources, track project tasks, and serve as the point of contact for ...

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How much do manager memory design engineer jobs pay per year?

As of Sep 11, 2026, the average yearly pay for manager memory design engineer in the United States is $134,466.00, according to ZipRecruiter salary data. Most workers in this role earn between $109,000.00 and $150,000.00 per year, depending on experience, location, and employer.

What does a manager memory design engineer do?

A Manager Memory Design Engineer oversees the development and design of memory components, such as DRAM, SRAM, and Flash, used in electronic devices. They lead a team of engineers, coordinate project timelines, and ensure the memory architecture meets performance, power, and reliability specifications. Their responsibilities also include collaborating with cross-functional teams, mentoring junior engineers, and staying updated with the latest advancements in memory technology. This role combines technical expertise in memory circuit design with leadership and project management skills.

What are the key skills and qualifications needed to thrive as a manager memory design engineer?

To thrive as a Manager Memory Design Engineer, you need a strong background in electrical engineering, experience with memory architecture, and expertise in circuit design, often supported by a relevant degree and years of industry experience. Familiarity with EDA tools like Cadence or Synopsys, and knowledge of industry standards such as DDR or SRAM/DRAM protocols, are typically required. Leadership, effective communication, and project management skills help you guide teams and collaborate across departments. These skills are crucial for delivering innovative, high-performance memory solutions on time and ensuring team and project success.

What are some common challenges faced by a manager memory design engineer and how can they be addressed?

Manager Memory Design Engineers often face challenges in balancing project timelines with the technical complexity of designing high-performance memory circuits. Coordinating cross-functional teams, such as layout, verification, and product engineering, can also be demanding, especially when requirements change or unexpected technical issues arise. Effective communication, proactive risk management, and fostering a collaborative team environment are key strategies for overcoming these obstacles. Staying updated with the latest memory technology trends and design tools also helps in anticipating and mitigating potential project bottlenecks.

What cities are hiring for Manager Memory Design Engineer jobs?

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What are the most commonly searched types of Memory Design Engineer jobs?

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What states have the most Manager Memory Design Engineer jobs?

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Manager Memory Design Engineer jobs near you

Memory Design Engineer

Troy, MI • On-site

Resource Point LLC
IT Services • 51 - 200 employees
Learn more about Resource Point LLCexternal

Contractor

Re-posted 20 days ago

Job description

Looking for W-2 CANDIDATES ONLY who are authorized to work in the United States without the need for sponsorship. H-1B Transfers AND CORP-TO-CORP Candidates WILL NOT BE CONSIDERED for this position

Job Title: Memory Design Engineer

Location: Ontario, Canada

Duration: 6+ Months with possible extension

Qualification Required:

  • Typically requires minimum of 2 to 5  years of experience in Memory Design with mainstream SRAM tools
  • Bachelors / Master Degree in E&E and E&C

Roles and Responsibilities:

  • Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis and Monte Carlo Simulations.
  • Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation.
  • Good experience in design verification: Sense amplifier analysis, self-time analysis and marginality analysis.
  • Good exposure to validation of the characterized data.
  • Strong knowledge of physical implementation impact on circuit performance.
  • Experience with the most advanced technology nodes up to 28nm and below.