ZipRecruiter

Log In

1

Manager Memory Design Engineer Jobs (NOW HIRING)

previous page

Showing results 41-60

All JobsMemory Design Engineer JobsManager Memory Design Engineer Jobs

Manager Memory Design Engineer information

See salary details

$52.5K

$134.5K

$207.5K

How much do manager memory design engineer jobs pay per year?

As of Sep 11, 2026, the average yearly pay for manager memory design engineer in the United States is $134,466.00, according to ZipRecruiter salary data. Most workers in this role earn between $109,000.00 and $150,000.00 per year, depending on experience, location, and employer.

What does a manager memory design engineer do?

A Manager Memory Design Engineer oversees the development and design of memory components, such as DRAM, SRAM, and Flash, used in electronic devices. They lead a team of engineers, coordinate project timelines, and ensure the memory architecture meets performance, power, and reliability specifications. Their responsibilities also include collaborating with cross-functional teams, mentoring junior engineers, and staying updated with the latest advancements in memory technology. This role combines technical expertise in memory circuit design with leadership and project management skills.

What are the key skills and qualifications needed to thrive as a manager memory design engineer?

To thrive as a Manager Memory Design Engineer, you need a strong background in electrical engineering, experience with memory architecture, and expertise in circuit design, often supported by a relevant degree and years of industry experience. Familiarity with EDA tools like Cadence or Synopsys, and knowledge of industry standards such as DDR or SRAM/DRAM protocols, are typically required. Leadership, effective communication, and project management skills help you guide teams and collaborate across departments. These skills are crucial for delivering innovative, high-performance memory solutions on time and ensuring team and project success.

What are some common challenges faced by a manager memory design engineer and how can they be addressed?

Manager Memory Design Engineers often face challenges in balancing project timelines with the technical complexity of designing high-performance memory circuits. Coordinating cross-functional teams, such as layout, verification, and product engineering, can also be demanding, especially when requirements change or unexpected technical issues arise. Effective communication, proactive risk management, and fostering a collaborative team environment are key strategies for overcoming these obstacles. Staying updated with the latest memory technology trends and design tools also helps in anticipating and mitigating potential project bottlenecks.

What cities are hiring for Manager Memory Design Engineer jobs?

Cities with the most Manager Memory Design Engineer job openings:

What are the most commonly searched types of Memory Design Engineer jobs?

The most popular types of Memory Design Engineer jobs are:

What states have the most Manager Memory Design Engineer jobs?

States with the most job openings for Manager Memory Design Engineer jobs include:

What are popular job titles related to Manager Memory Design Engineer jobs?

For Manager Memory Design Engineer jobs, the most frequently searched job titles are:

Manager Memory Design Engineer jobs near you

DRAM Memory Design Engineer - Principal | MTS | SMTS

Boise, ID • On-site

Micron Technology, Inc
Semiconductor and Electronic Component Manufacturing • 10K+ employees
Learn more about Micron Technology, Incexternal

Other

Medical, Dental, Vision, PTO

Posted 28 days ago

Micron Technology rating

8.6

Company rating: 8.6 out of 10

Based on 43 frontline employees who took The Breakroom Quiz

Job description

DRAM Memory Design Engineer - Principal | MTS | SMTS

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

We are shaping the memory technologies that power today's most advanced computing platforms, from AI accelerators to mobile and client devices. Our DRAM Engineering team brings together skilled engineers across the globe to solve complex technical challenges, drive innovation, and deliver high-performance memory solutions. If you enjoy tackling difficult problems and turning ideas into products, you'll find exciting opportunities to make an impact here.

Responsibilities:
  • Design and optimize digital and analog circuits for next-generation DRAM products, including memory arrays, control logic, datapaths, address decoding, and I/O circuitry.
  • Lead circuit development, simulation, verification, and silicon validation to achieve performance, power, area, and quality targets.
  • Drive floor-planning, layout optimization, parasitic analysis, and tape-out activities.
  • Advance AI-assisted design, automation, and design-space exploration through collaboration with internal and external partners.
  • Provide technical leadership through innovation, multi-functional collaboration, and mentorship of other engineers.
Minimum Qualifications:
  • Bachelor's degree in Electrical Engineering or related field, plus MSEE with 10+ years, BSEE with 12+ years, or equivalent relevant semiconductor design experience; SMTS candidates typically have 15+ years of experience with demonstrated technical leadership.
  • Extensive knowledge of CMOS circuit design, device physics, state machine logic, and design verification methodologies.
  • Experience with Verilog modeling, simulation tools, and power delivery network (PDN) analysis.
  • Proficiency in scripting languages such as Python, Tcl, or Perl.
  • Strong analytical, problem-solving, communication, and multi-functional collaboration skills.
Preferred Qualifications:
  • Master's degree or PhD in Electrical Engineering or a related field.
  • Experience with DDR5, LPDDR5/LPDDR6, GDDR6/7, or HBM3/HBM4 memory technologies.
  • Experience with FINESIM, HSPICE, or similar schematic entry and simulation tools.
  • Experience leading complex circuit design projects and mentoring engineers.
  • Exposure to AI/ML-assisted design flows, agentic AI, or advanced design automation frameworks.

Work location: Boise, ID, Main Site. Schedule is 5 days onsite. Relocation support may be available.

Job Profile(s):

Semiconductor Design Engineer 5 - Semiconductor Design Eng SMTS

Relocation Level: TBD

Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future.

  • We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.
  • Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.
  • Additionally, Micron benefits include a robust paid time-off program and paid holidays.

For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

#J-18808-Ljbffr

What Micron Technology employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom

Apply