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Manager Memory Design Engineer Jobs (NOW HIRING)

Intel Corporation

Memory Circuit Design Engineer

Austin, TX · On-site

$190K - $269K/yr

The CPU Circuit Technology team is looking for a highly motivated and experienced individual to join our team as a Memory Circuit Design Engineer. In this role, you will be responsible for designing ...

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How much do manager memory design engineer jobs pay per year?

As of Aug 22, 2026, the average yearly pay for manager memory design engineer in the United States is $134,466.00, according to ZipRecruiter salary data. Most workers in this role earn between $109,000.00 and $150,000.00 per year, depending on experience, location, and employer.

What does a manager memory design engineer do?

A Manager Memory Design Engineer oversees the development and design of memory components, such as DRAM, SRAM, and Flash, used in electronic devices. They lead a team of engineers, coordinate project timelines, and ensure the memory architecture meets performance, power, and reliability specifications. Their responsibilities also include collaborating with cross-functional teams, mentoring junior engineers, and staying updated with the latest advancements in memory technology. This role combines technical expertise in memory circuit design with leadership and project management skills.

What are the key skills and qualifications needed to thrive as a manager memory design engineer?

To thrive as a Manager Memory Design Engineer, you need a strong background in electrical engineering, experience with memory architecture, and expertise in circuit design, often supported by a relevant degree and years of industry experience. Familiarity with EDA tools like Cadence or Synopsys, and knowledge of industry standards such as DDR or SRAM/DRAM protocols, are typically required. Leadership, effective communication, and project management skills help you guide teams and collaborate across departments. These skills are crucial for delivering innovative, high-performance memory solutions on time and ensuring team and project success.

What are some common challenges faced by a manager memory design engineer and how can they be addressed?

Manager Memory Design Engineers often face challenges in balancing project timelines with the technical complexity of designing high-performance memory circuits. Coordinating cross-functional teams, such as layout, verification, and product engineering, can also be demanding, especially when requirements change or unexpected technical issues arise. Effective communication, proactive risk management, and fostering a collaborative team environment are key strategies for overcoming these obstacles. Staying updated with the latest memory technology trends and design tools also helps in anticipating and mitigating potential project bottlenecks.

What cities are hiring for Manager Memory Design Engineer jobs?

Cities with the most Manager Memory Design Engineer job openings:

What are the most commonly searched types of Memory Design Engineer jobs?

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What states have the most Manager Memory Design Engineer jobs?

States with the most job openings for Manager Memory Design Engineer jobs include:

Manager Memory Design Engineer jobs near you

Memory Circuit Design Engineer

TetraMem INC

Fremont, CA

Full-time

Medical, Retirement, PTO

Re-posted 14 days ago

Job description

Company Description

TetraMem is a fast-growing well-funded startup company working on the next generation of computing platforms with unique ReRAM-based in-memory computing technologies. We are hiring in multiple positions from software to hardware.

We offer a very competitive compensation, commensurate with experience, and a full benefits package including medical, professional PTO, 401k, and other perks.

Job Description
  • Design the memory IC projects from concept to tape-out
  • Define and implement memory architectures and circuits, optimizing for speed, power, and area.
  • Develop comprehensive test plans, simulate designs, and debug issues.
  • Work on performance improvements, analyzing and addressing bottlenecks in memory designs.
  • Work closely with other engineering teams, such as analog and digital, to ensure seamless integration with overall product development.
  • Investigate and resolve design issues and participate in silicon bring-up and validation activities.
Qualifications

  • MS or PhD in Electrical Engineering with emphasis on CMOS memory, digital or mixed-signal design

  • 5+ years of experience in circuit design in advanced CMOS processes (PhD experience may be considered as experience), successful tape-out experience with leading foundries

  • Experience in memory circuit design in one of: SRAM, DRAM, Flash or emerging NVM technologies

  • Strong understanding of layout design including layout dependent effects, pitch matching, and design for manufacturing

  • Familiar with common EDA environment tools, CAD tools and memory design methodology including design, simulation, layout, and verification tools (e.g. Synopsys Cadence, Mentor Graphics etc.).

  • Ability to create innovative architecture and circuit solutions to customer requirements

  • Ability to work in startup environment and work both independently and as a team player

Experience in one or more of the following areas considered a strong plus:

  • Hands-on production experience with key memory blocks such as sense amplifier, charge pump, read/write assist circuit, PVT tracker, power gating etc

  • Familiar with memory controller or memory interface

  • Experience with emerging non-volatile memory

Additional Information

All your information will be kept confidential according to EEO guidelines.

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