... Engineering, or a related discipline. Technical Experience: * Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between ...
... Engineering, or a related discipline. Technical Experience: * Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between ...
Digital Design Engineer
$90K - $100K/yr
Digital Design Engineer - Secret Clearance Required Location: Tucson, AZ (On-site) Job Type: W-2 ... Memory components * Work with industry-standard interfaces such as: * PCIe * Ethernet * I2C, SPI ...
Digital Design Engineer
$90K - $100K/yr
Digital Design Engineer - Secret Clearance Required Location: Tucson, AZ (On-site) Job Type: W-2 ... Memory components * Work with industry-standard interfaces such as: * PCIe * Ethernet * I2C, SPI ...
Compensation open to negotiation Digital Design Engineer Responsible for the design, analysis ... memory, and industry interfaces, such as PCIe, Ethernet, I2C, SPI, and UART. The candidate will be ...
Compensation open to negotiation Digital Design Engineer Responsible for the design, analysis ... memory, and industry interfaces, such as PCIe, Ethernet, I2C, SPI, and UART. The candidate will be ...
Digital Design Engineer
Tucson, AZ · On-site
$90K - $100K/yr
Digital Design Engineer - Secret Clearance Required Location: Tucson, AZ (On-site) Job Type: W-2 ... Memory components * Work with industry-standard interfaces such as: * PCIe * Ethernet * I2C, SPI ...
Digital Design Engineer
Tucson, AZ · On-site
$90K - $100K/yr
Digital Design Engineer - Secret Clearance Required Location: Tucson, AZ (On-site) Job Type: W-2 ... Memory components * Work with industry-standard interfaces such as: * PCIe * Ethernet * I2C, SPI ...
Digital Design Engineer
$90K - $100K/yr
Digital Design Engineer - Secret Clearance Required Location: Tucson, AZ (On-site) Job Type: W-2 ... Memory components * Work with industry-standard interfaces such as: * PCIe * Ethernet * I2C, SPI ...
Quick apply
Digital Design Engineer
$90K - $100K/yr
Digital Design Engineer - Secret Clearance Required Location: Tucson, AZ (On-site) Job Type: W-2 ... Memory components * Work with industry-standard interfaces such as: * PCIe * Ethernet * I2C, SPI ...
Digital Design Engineer
Tucson, AZ · On-site
$128K/yr
... memory, and industry interfaces, such as PCIe, Ethernet, I2C, SPI, and UART. The candidate will be ... of engineering digital circuit design experience to include at least 2 of the following:
Digital Design Engineer
Tucson, AZ · On-site
$128K/yr
... memory, and industry interfaces, such as PCIe, Ethernet, I2C, SPI, and UART. The candidate will be ... of engineering digital circuit design experience to include at least 2 of the following:
Digital Design Engineer with Security Clearance
Tucson, AZ · On-site
$70K - $85K/yr
... Memory devices o Industry-standard interfaces (PCIe, Ethernet, I2C, SPI, UART) • Support multi-assembly system/unit design efforts • Collaborate within a cross-functional engineering team ...
Digital Design Engineer with Security Clearance
Tucson, AZ · On-site
$70K - $85K/yr
... Memory devices o Industry-standard interfaces (PCIe, Ethernet, I2C, SPI, UART) • Support multi-assembly system/unit design efforts • Collaborate within a cross-functional engineering team ...
Support development of hardware designs involving processors, FPGAs, memory, and digital interface ... Work cross-functionally with engineering teams to resolve design, integration, and test issues.
Support development of hardware designs involving processors, FPGAs, memory, and digital interface ... Work cross-functionally with engineering teams to resolve design, integration, and test issues.
Support development of hardware designs involving processors, FPGAs, memory, and digital interface ... Work cross-functionally with engineering teams to resolve design, integration, and test issues.
Support development of hardware designs involving processors, FPGAs, memory, and digital interface ... Work cross-functionally with engineering teams to resolve design, integration, and test issues.
The engineer will support complex, multi-layer circuit card assemblies involving processors, FPGAs, memory devices, and high-speed digital interfaces. Key Responsibilities * Design, analyze, simulate ...
The engineer will support complex, multi-layer circuit card assemblies involving processors, FPGAs, memory devices, and high-speed digital interfaces. Key Responsibilities * Design, analyze, simulate ...
The engineer will support complex, multi-layer circuit card assemblies involving processors, FPGAs, memory devices, and high-speed digital interfaces. Key Responsibilities * Design, analyze, simulate ...
The engineer will support complex, multi-layer circuit card assemblies involving processors, FPGAs, memory devices, and high-speed digital interfaces. Key Responsibilities * Design, analyze, simulate ...
Support development of hardware designs involving processors, FPGAs, memory, and digital interface ... Work cross-functionally with engineering teams to resolve design, integration, and test issues.
Support development of hardware designs involving processors, FPGAs, memory, and digital interface ... Work cross-functionally with engineering teams to resolve design, integration, and test issues.
The engineer will support complex, multi-layer circuit card assemblies involving processors, FPGAs, memory devices, and high-speed digital interfaces. Key Responsibilities Design, analyze, simulate ...
The engineer will support complex, multi-layer circuit card assemblies involving processors, FPGAs, memory devices, and high-speed digital interfaces. Key Responsibilities Design, analyze, simulate ...
Digital Design Engineer 102091 with Security Clearance
Tucson, AZ · On-site
$116K/yr
Digital Design Engineer Location: Tucson, AZ Required Clearance: Secret Since 1999, ITEC has been a ... memory, and industry interfaces, such as PCIe, Ethernet, I2C, SPI, and UART. The candidate will be ...
Digital Design Engineer 102091 with Security Clearance
Tucson, AZ · On-site
$116K/yr
Digital Design Engineer Location: Tucson, AZ Required Clearance: Secret Since 1999, ITEC has been a ... memory, and industry interfaces, such as PCIe, Ethernet, I2C, SPI, and UART. The candidate will be ...
Digital Design Engineer with Security Clearance
Tucson, AZ · On-site
$126K/yr
... memory, and industry interfaces, such as PCIe, Ethernet, I2C, SPI, and UART. The candidate will be ... of engineering digital circuit design experience to include at least 2 of the following:
Digital Design Engineer with Security Clearance
Tucson, AZ · On-site
$126K/yr
... memory, and industry interfaces, such as PCIe, Ethernet, I2C, SPI, and UART. The candidate will be ... of engineering digital circuit design experience to include at least 2 of the following:
Digital Design Engineer with Security Clearance
Tucson, AZ · On-site
$126K/yr
... memory, and industry interfaces, such as PCIe, Ethernet, I2C, SPI, and UART. The candidate will be ... of engineering digital circuit design experience to include at least 2 of the following:
Digital Design Engineer with Security Clearance
Tucson, AZ · On-site
$126K/yr
... memory, and industry interfaces, such as PCIe, Ethernet, I2C, SPI, and UART. The candidate will be ... of engineering digital circuit design experience to include at least 2 of the following:
Digital Design Engineer - P3 - Cleared Onsite MAT Ramp with Security Clearance
Tucson, AZ · On-site
$116K/yr
The Digital Design Engineer is responsible for the design, analysis, simulation, test, and ... memory, and industry interfaces, such as PCIe, Ethernet, I2C, SPI, and UART. The candidate will be ...
Digital Design Engineer - P3 - Cleared Onsite MAT Ramp with Security Clearance
Tucson, AZ · On-site
$116K/yr
The Digital Design Engineer is responsible for the design, analysis, simulation, test, and ... memory, and industry interfaces, such as PCIe, Ethernet, I2C, SPI, and UART. The candidate will be ...
Digital Design Engineer - P4 - Cleared On-Site MAT Ramp with Security Clearance
Tucson, AZ · On-site
$116K/yr
The Digital Design Engineer is responsible for the design, analysis, simulation, test, and ... memory, and industry interfaces, such as PCIe, Ethernet, I2C, SPI, and UART. The candidate will be ...
Digital Design Engineer - P4 - Cleared On-Site MAT Ramp with Security Clearance
Tucson, AZ · On-site
$116K/yr
The Digital Design Engineer is responsible for the design, analysis, simulation, test, and ... memory, and industry interfaces, such as PCIe, Ethernet, I2C, SPI, and UART. The candidate will be ...
The Digital Design Engineer is responsible for the design, analysis, simulation, test, and ... memory, and industry interfaces, such as PCIe, Ethernet, I2C, SPI, and UART. The candidate will be ...
The Digital Design Engineer is responsible for the design, analysis, simulation, test, and ... memory, and industry interfaces, such as PCIe, Ethernet, I2C, SPI, and UART. The candidate will be ...
Digital Design Engineer with Security Clearance
Tucson, AZ · On-site
$126K/yr
Digital Design Engineer Location: Tucson, AZ Job ID: #72749 Pay Range: $50-62 12 month contract ... memory, and industry interfaces, such as PCIe, Ethernet, I2C, SPI, and UART. The candidate will be ...
New
Digital Design Engineer with Security Clearance
Tucson, AZ · On-site
$126K/yr
Digital Design Engineer Location: Tucson, AZ Job ID: #72749 Pay Range: $50-62 12 month contract ... memory, and industry interfaces, such as PCIe, Ethernet, I2C, SPI, and UART. The candidate will be ...
New
Memory Design Engineer information
See Arizona salary details
$89.4K is the 25th percentile. Wages below this are outliers.
$75K - $92.8K
31% of jobs
$92.8K - $110.6K
5% of jobs
The median wage is $123.4K / yr.
$110.6K - $128.4K
19% of jobs
$142.1K is the 75th percentile. Wages above this are outliers.
$128.4K - $146.2K
26% of jobs
$146.2K - $164K
13% of jobs
$164K - $181.8K
4% of jobs
$181.8K - $199.6K
0% of jobs
$199.6K - $217.3K
0% of jobs
$217.3K - $235.1K
0% of jobs
$235.1K - $252.9K
1% of jobs
$252.9K - $270.7K
1% of jobs
$75K
$131.7K
$270.7K
How much do memory design engineer jobs pay per year?
What are the primary challenges faced by Memory Design Engineers on a daily basis?
Memory Design Engineers often encounter challenges such as optimizing memory circuits for speed, power efficiency, and area while ensuring manufacturability and meeting reliability standards. Balancing these conflicting requirements requires strong analytical skills and close collaboration with verification, process, and layout teams. The role also involves troubleshooting design issues, staying updated with evolving semiconductor technologies, and ensuring timely project delivery. Overcoming these challenges fosters professional development and helps engineers build a solid track record in advanced technology nodes.
What are the key skills and qualifications needed to thrive in the Memory Design Engineer position, and why are they important?
A Memory Design Engineer requires a strong background in electrical engineering, semiconductor physics, and digital/analog circuit design, typically supported by a relevant bachelor's or master's degree. Expertise with EDA tools like Cadence, Synopsys, or Mentor Graphics, and familiarity with scripting languages and memory characterization tools is essential. Strong problem-solving skills, attention to detail, and effective communication are important soft skills in this role. These competencies are crucial to ensure reliable, high-performance memory designs that meet rigorous industry standards and enable smooth collaboration within multidisciplinary engineering teams.
What engineers make $500,000?
What does a memory design engineer do?
What is the salary of memory layout design engineer?
What is a Memory Design Engineer job?
A Memory Design Engineer is responsible for designing, developing, and optimizing memory circuits such as SRAM, DRAM, or flash memory. They work on transistor-level design, layout, simulation, and verification to ensure performance, power efficiency, and reliability. Engineers collaborate with process, verification, and product teams to meet design specifications and manufacturing constraints. Their role is critical in advancing memory technology for applications in consumer electronics, computing, and enterprise solutions.
What jobs can DT get you?
Intel rating
8.7
Based on 144 frontline employees who took The Breakroom Quiz
10th of 139 rated electronics manufacturers
Job description
The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.
The Advanced Design (AD) team is part of Intel's larger Design Technology Platform (DTP) Organization and is focused on pathfinding and development of advanced memory technology. These circuits enable best-in-class memory collateral, IP and innovative product design across all generations of Intel process technology. At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable Intel's internal and external customers to get to the market faster with products that include high-performance, high-density, low-power memory at the leading edge of the technology curve and implemented in Intel's advanced CMOS process technologies.
You will be partnering with and leveraging domain experts across various areas of technology development, EDA vendors and product design teams to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on Intel advanced CMOS process technologies. In this position your responsibilities will include, but may not be limited to:
- Memory pathfinding activities and power, performance and area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement.
- Memory bit-cell and complex periphery IC layout and automation.
- Memory array/IP design, memory circuit innovation, test-chip design.
- Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp.
You must possess the minimum qualifications listed below to interview for this position. Preferred qualifications are not required but may work to your advantage during the interview process.
Minimum Qualifications:
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline, including 4+ years of professional experience gained through either internships or full-time employment Or a PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline.
Technical Experience:
- Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM.
- Design trade-offs between power, performance, and area (PPA).
- Custom digital circuit design, simulation, layout design, and verification.
- Knowledge of EDA tools used for custom digital and memory circuit design.
Preferred Qualifications:
- PhD with 1-2 years of professional experience gained through either internships or full-time employment.
- Design technology co-optimization (DTCO).
- Post-Si validation experience.
- Knowledge of the CMOS ASIC design flow.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968