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Intern Memory Design Engineer Jobs (NOW HIRING)

Intel

Memory Circuit Design Engineer

Phoenix, AZ

... Engineering, or a related discipline. Technical Experience: * Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between ...

Intel

Memory Circuit Design Engineer

Hillsboro, OR

... Engineering, or a related discipline. Technical Experience: * Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between ...

Intel

Memory Circuit Design Engineer

Austin, TX

... Engineering, or a related discipline. Technical Experience: * Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between ...

Intel

Memory Circuit Design Engineer

Santa Clara, CA

... Engineering, or a related discipline. Technical Experience: * Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between ...

Micron

Staff Design Engineer, HBM

Richardson, TX · On-site

As an HBM Memory Design Engineer - Sustaining (Staff) , you will work closely with cross-functional teams including Design Engineering (DE), Product Engineering (PE), Process Integration, Packaging ...

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How much do intern memory design engineer jobs pay per hour?

As of Jul 30, 2026, the average hourly pay for intern memory design engineer in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.

What are some common challenges faced by an Intern Memory Design Engineer during their internship?

As an Intern Memory Design Engineer, you may encounter challenges such as understanding complex circuit design concepts and adapting to industry-standard Electronic Design Automation (EDA) tools. Working in this role often involves collaborating closely with experienced engineers and cross-functional teams to verify and optimize memory layouts for performance and reliability. Navigating the steep learning curve and balancing hands-on project work with ongoing training can be demanding, but these experiences are invaluable for building foundational skills and industry knowledge.

What does an Intern Memory Design Engineer do?

An Intern Memory Design Engineer assists in the design, development, and testing of computer memory components such as DRAM, SRAM, or Flash memory. They work closely with senior engineers to create circuit schematics, run simulations, analyze data, and help optimize memory performance. Interns may also participate in debugging and validation of memory products, learning industry-standard design tools and methodologies. This role provides valuable hands-on experience in semiconductor design and the opportunity to contribute to real-world projects.

What are the key skills and qualifications needed to thrive as an Intern Memory Design Engineer, and why are they important?

To thrive as an Intern Memory Design Engineer, you need a solid background in electrical engineering, digital/analog circuit design, and semiconductor fundamentals, often supported by ongoing or completed coursework toward a relevant degree. Familiarity with EDA tools such as Cadence, Synopsys, or Mentor Graphics, and basic knowledge of scripting languages like Python or TCL, are typically required. Strong analytical thinking, attention to detail, and effective communication set standout interns apart in collaborative engineering environments. These skills and qualities are crucial for designing reliable memory components and contributing efficiently to complex, team-driven projects.
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Intern Memory Design Engineer jobs near you
Infographic showing various Intern Memory Design Engineer job openings in the United States as of July 2026, with employment types broken down into 88% Full Time, 9% Part Time, and 3% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $40,304 per year, or $19.4 per hour.

SSG Design Engineering Intern (Fall 2026)

Cadence Design Systems, Inc.

San Jose, CA

$35/hr

Full-time

Posted 13 days ago

Cadence Design Systems rating

9.0

Company rating: 9.0 out of 10

Based on 5 frontline employees who took The Breakroom Quiz

33rd of 246 rated software companies

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design Engineering Intern
The Cadence Silicon Solutions Group (SSG) is seeing rapid adoption of our industry leading Digital IP (intellectual Property), from processor cores and DSPs to Memory Controllers, to Network on Chip (NoC), to IO solutions. Our configurable and extensible IP solutions are designed to meet the demands of SOCs and Chiplets targeted at a wide range of applications. Our customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.


The Cadence SSG Team is hiring graduates to join our R&D teams in San Jose, CA. This is an amazing opportunity to work as a Design Engineering Intern at a world leader in computational software, semiconductor design IP, and system verification hardware. Come be part of this great SSG Team where you can make an impact that is visible.
This Design Engineering Intern position involves working on Digital Design tasks, or Design Verification tasks related to the Janus NoC IP product.


(a) Digital Design projects involve working on aspects of the logic design of the Janus NoC. It can involve RTL implementation of a specified micro-architecture in System Verilog, simulating and debugging RTL logic, running synthesis, place & route and other Electronic Design Automation (EDA) tools to study and achieve timing, area, and power goals.


(b) Design Verification Team projects involve working on aspects of the verification of the Janus NoC. Assist with developing test plans, writing functional tests (UVM) and verification monitors (SVA) UVM/SVA monitors, debugging failures, analyzing coverage information, and scripting Design Verification flows.

The Design Engineering intern will work closely with the Design, Verification, and Physical Design teams.


Position Requirements:
Currently enrolled in MS/BS program with major in Electrical Engineering, Computer Engineering, or a similar major.
Deep understanding of Digital Design and/or Design Verification Fundamentals
Excellent automation skills using Tcl, Perl, shell scripting
Excellent oral and written communications skills
Exposure to design automation tools is a plus

Internship will be based in San Jose location. Ideal candidates should be from local school near office.

The annual salary range for California is $35/hr to $62/hr. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

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