ZipRecruiter

Log In

2

Full Time Uvm Verification Jobs (NOW HIRING)

Verilab

Design Verification Engineer

Austin, TX · On-site

$134.80K - $164.50K/yr

As a permanent full-time employee of Verilab, you will be responsible for all aspects of ... C/C++ developing, or integrating, reference models into SystemVerilog/UVM environments. * Formal ...

AVTC Group

Senior FPGA Engineer (DOD cleared)

Tucson, AZ · On-site

$122.90K - $157.90K/yr

... Full Time W-2 or Contract Rate: open to Negotiation Benefits: including Health, Dental Vision, PTO ... SystemVerilog / UVM verification experience. * Experience with emulation platforms such as Veloce.

Chipton Ross

FPGA Design Engineer

Sunnyvale, CA · On-site

$144.40K - $198.90K/yr

Verifying FPGA and/or ASIC designs including creating UVM verification environments, testbenches ... Accredited HSD/GED WORK HOURS * Full-Time * 5/40 work schedule * 1st Shift ADDITIONAL INFORMATION

E-Space

Staff DV Engineer

Saratoga, CA · On-site

$120K - $220K/yr

... existing UVM verification environment · Solid understanding of UVM architecture and methodology ... a full time, exempt position, based out of our Saratoga office. The target base pay for this ...

Lightmatter

Sr Staff Design Verification

Mountain View, CA · On-site

$224K - $257K/yr

Your role will involve close collaboration with our digital design experts, using UVM testbench ... Equity grants (applicable to full-time employees) Benefits eligibility may vary depending on your ...

E-Space

Staff DV Engineer

Saratoga, CA

$120K - $220K/yr

... existing UVM verification environment Solid understanding of UVM architecture and methodology ... a full time, exempt position, based out of our Saratoga office. The target base pay for this ...

E-Space

Staff DV Engineer

Saratoga, CA · On-site

$120K - $220K/yr

... UVM verification environment • Solid understanding of UVM architecture and methodology ... a full time, exempt position, based out of our Saratoga office. The target base pay for this ...

Google

CPU Design Verification Engineer

Mountain View, CA · On-site

$160.40K - $195.80K/yr

Experience with Universal Verification Methodology (UVM), SystemVerilog, or other scripting ... The US base salary range for this full-time position is $138,000-$198,000 bonus equity benefits.

next page

Showing results 1-20

People also search for

All JobsFull Time Uvm Verification Jobs

Full Time Uvm Verification information

See salary details

$80K

$142.6K

$203.5K

How much do full time uvm verification jobs pay per year?

As of May 31, 2026, the average yearly pay for full time uvm verification in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Full Time UVM Verification Engineer, and why are they important?

To thrive as a Full Time UVM Verification Engineer, you need a strong background in digital design, verification methodologies, and proficiency in SystemVerilog, often supported by a degree in electrical or computer engineering. Familiarity with Universal Verification Methodology (UVM) libraries, EDA tools like Synopsys VCS or Cadence Incisive, and scripting languages such as Python or Perl is typically essential. Analytical thinking, attention to detail, and effective communication are standout soft skills for this position. These skills and qualifications ensure the creation of robust testbenches, effective bug detection, and efficient collaboration within hardware design teams.

What are some common challenges faced by Full Time UVM Verification engineers, and how can they be addressed?

Full Time UVM Verification engineers often encounter challenges such as managing complex testbench architectures, debugging intricate simulation failures, and keeping up with evolving verification methodologies. To address these, engineers frequently collaborate closely with design teams to clarify specifications and root-cause issues, utilize advanced debugging tools, and participate in continuous learning through workshops and documentation. Adopting systematic approaches to test planning and leveraging reusable UVM components can also help streamline the verification process and enhance productivity.

What are Full Time UVM Verification Engineers?

Full Time UVM Verification Engineers are professionals who specialize in verifying the functionality and performance of integrated circuit (IC) designs using the Universal Verification Methodology (UVM). They work as permanent staff members within semiconductor or electronics companies to develop, implement, and maintain advanced verification environments for digital hardware designs. Their role involves writing testbenches, creating reusable verification components, running simulations, and debugging issues to ensure the design meets specifications before fabrication. These engineers collaborate with design and systems teams to deliver high-quality, reliable products. UVM Verification Engineers are crucial in reducing design errors and improving time-to-market for complex chips.

What is the difference between Full Time Uvm Verification vs Full Time Uvm Developer?

AspectFull Time Uvm VerificationFull Time Uvm Developer
Primary RoleDesigning and executing UVM testbenches for verificationDeveloping UVM-based verification environments and tools
Skills & CertificationsUVM, SystemVerilog, verification methodologiesUVM, SystemVerilog, coding and scripting skills
Work EnvironmentVerification teams in semiconductor or chip design companiesVerification and design teams in similar industries

Full Time Uvm Verification focuses on creating and running testbenches to verify hardware designs, while Full Time Uvm Developer emphasizes developing verification tools and environments. Both roles require strong SystemVerilog and UVM skills, but verification roles are more testing-oriented, whereas development roles involve building verification infrastructure.

More about Full Time Uvm Verification jobs
What cities are hiring for Full Time Uvm Verification jobs? Cities with the most Full Time Uvm Verification job openings:
What are the most commonly searched types of Uvm Verification jobs? The most popular types of Uvm Verification jobs are:
What states have the most Full Time Uvm Verification jobs? States with the most job openings for Full Time Uvm Verification jobs include:
What job categories do people searching Full Time Uvm Verification jobs look for? The top searched job categories for Full Time Uvm Verification jobs are:
Full Time Uvm Verification jobs near you
Sr Design Verification Engineer ( Redmond WA - Onsite)

Sr Design Verification Engineer ( Redmond WA - Onsite)

Encore Semi, Inc.

Redmond, WA • On-site

$150K - $165K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Posted 9 days ago

Job description

Sr Design Verification Engineer (Remote)
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: US citizen or Lawful Permanent Resident.
Location: Redmond WA
Digital ASIC Verification Engineer
We are looking for an experienced Digital ASIC Verification Engineer to verify complex digital systems, including ARM-based CPUs and DSP blocks. You will own the full verification lifecycle, from test planning to coverage closure using SystemVerilog and UVM.
Responsibilities
  • Develop UVM/SystemVerilog testbenches for block and system-level verification
  • Create and execute test plans; drive functional and code coverage closure
  • Automate test generation and regressions using Python and MATLAB
  • Support pre-silicon verification and post-silicon bring-up
  • Collaborate across teams to ensure design quality and integrity

Qualifications
  • 10+ years of ASIC verification experience
  • Strong skills in SystemVerilog, UVM, and constrained random verification
  • Familiarity with ARM/CPU architecture and OOP concepts
  • Proficiency in Python scripting (MATLAB a plus)
  • Bachelors in EE/CS/CE (Master's preferred)

The anticipated annual base salary for this position is between $150,000 to $165,000, which also includes a comprehensive benefits package.
Full-Time Benefits:
• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
• Dental & Vision: Company covers 50% of premiums for Employee and Dependents
• Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
• Employee Assistant Program (EAP)
• 401k - Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
LinkedIn :: https://www.linkedin.com/in/rtl2gds/

Apply