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Director Asic Design Jobs (NOW HIRING)

Cisco

ASIC Design Verification Engineer

San Jose, CA · On-site

$165K - $241K/yr

Develop simulation models, test plans, direct and random tests, code or functional coverage, multi ... Experience with ASIC design and verification processes, debugging, methodology, and tools.

K2 Space

OR · On-site

$130K - $200K/yr

The Role We are seeking an ASIC Design Verification Engineer whose role will be to verify the ... Drive constrained-random and directed testing strategies to validate functionality, corner cases ...

Cisco

ASIC Design Verification Engineer

San Jose, CA

$165K - $241K/yr

Develop simulation models, test plans, direct and random tests, code or functional coverage, multi ... Experience with ASIC design and verification processes, debugging, methodology, and tools.

K2 Space

Senior ASIC Design Verification Engineer

$170K - $250K/yr

The Role We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the ... Drive constrained-random and directed testing strategies to validate functionality, corner cases ...

Trinity Technology Solutions

ASIC Engineer

San Jose, CA · On-site

$194K/yr

... Direct Hire About the job: Senior ASIC Engineer San Jose, CA-onsite $230k Our client, a cutting-edge developer of custom ASICs and SoCs for emerging technologies, is seeking a Senior ASIC Design ...

Cisco

ASIC Design Verification Engineer

San Jose, CA

$152K - $219K/yr

Your Impact As an ASIC Design Verification Engineer, you will play a critical role in developing ... directed stimulus. * Ensure comprehensive verification coverage through code and functional ...

Positron AI

ASIC Design Verification Engineer

$200K - $350K/yr

Role Overview As an ASIC Design Verification Engineer, you will play a critical role in ensuring ... Create and maintain simulation testbenches, directed and constrained-random tests * Collaborate ...

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How much do director asic design jobs pay per year?

As of Jun 9, 2026, the average yearly pay for director asic design in the United States is $135,763.00, according to ZipRecruiter salary data. Most workers in this role earn between $109,500.00 and $163,000.00 per year, depending on experience, location, and employer.
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Director Asic Design jobs near you
Infographic showing various Director Asic Design job openings in the United States as of May 2026, with employment types broken down into 84% Full Time, 14% Part Time, 1% Temporary, and 1% Contract. Highlights an 86% Physical, 9% Hybrid, and 5% Remote job distribution, with an average salary of $135,763 per year, or $65.3 per hour.
ASIC/SoC Design Engineer, RTL design for SoC IPs

ASIC/SoC Design Engineer, RTL design for SoC IPs

Advanced Micro Devices, Inc

San Jose, CA • On-site

$145K/yr

Full-time

Posted 29 days ago

Advanced Micro Devices rating

8.4

Company rating: 8.4 out of 10

Based on 7 frontline employees who took The Breakroom Quiz

24th of 139 rated electronics manufacturers

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
Join AMD's Silicon Design team to design and develop cutting-edge IPs for next-generation embedded products. As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design.
THE PERSON:
The ideal candidate is a seasoned ASIC/SOC designer with proven expertise across the entire chip development lifecycle-from RTL design through silicon bring-up. You excel in Verilog RTL coding, timing closure, and physical design awareness. With multiple production tape-outs under your belt, you bring deep technical expertise, strong ownership, and the ability to mentor junior engineers while driving projects to successful completion.
KEY RESPONSIBILITIES:
  • RTL Design & Microarchitecture: Author detailed micro-architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA (Performance, Power, Area) targets and timing requirements.
  • Full ASIC Development Lifecycle: Drive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, timing analysis, verification, physical design integration, and post-silicon validation.
  • Timing Closure & Optimization: Develop and maintain timing constraints (SDC), perform static timing analysis (STA) using industry-standard tools (PrimeTime/Tempus), resolve timing violations, and collaborate with physical design to achieve timing closure.
  • SOC Integration: Integrate complex ASIC IP blocks into full-chip SOC environment, ensuring proper connectivity, clock domain crossings, and interface compliance with industry-standard protocols (AMBA AXI/AHB/APB, PCIe, CXL).
  • Design Quality & Verification: Partner with verification teams to ensure comprehensive functional coverage; implement design-for-test (DFT) and design-for-debug (DFD) features; participate in RTL quality reviews and signoff.
  • Physical Design Collaboration: Work closely with physical design engineers on floor planning, placement constraints, clock tree synthesis, and power grid design to ensure timing convergence and manufacturing readiness.
  • Automation & Productivity: Develop Python/Perl/Tcl scripts to automate repetitive tasks, improve design quality checks, and enhance team efficiency throughout the design flow.
  • Cross-Functional Collaboration: Engage with architecture, verification, physical design, CAD, and post-silicon teams to resolve complex technical challenges and deliver high-quality silicon on schedule.

REQUIRED QUALIFICATIONS:
  • Proven track record with 2+ production ASIC tape-outs in senior design roles
  • Expert-level Verilog RTL coding skills with deep understanding of synthesizable RTL constructs and coding best practices
  • Hands-on experience with the complete ASIC design flow: RTL • Synthesis • STA • Physical Design • Tape-out
  • Experience writing and debugging SDC timing constraints, including multi-cycle paths, false paths, and clock domain crossing constraints
  • Experience integrating complex IP blocks into SOC designs
  • Knowledge of industry-standard on-chip interconnect protocols (AMBA AXI/AHB/APB)
  • Bachelor's or Master's degree in Electrical Engineering or Computer Engineering

PREFERRED QUALIFICATIONS:
  • Knowledge of ARM architecture and AMBA protocol specifications
  • Familiarity with PCIe or CXL transaction layer protocols
  • Experience with low-power design techniques (clock gating, power gating, voltage scaling)
  • Proficiency in scripting languages: Python, Perl, Tcl, or Shell scripting
  • Exposure to formal verification tools for equivalence checking and property verification
  • Familiarity with AI-assisted design tools and modern EDA technologies
  • Experience mentoring junior engineers and leading design teams
  • Strong technical writing skills for design specifications and documentation
  • Excellent communication and collaboration skills in cross-functional environments

LOCATION: San Jose, CA
This role is not eligible for visa sponsorship.
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Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.
This posting is for an existing vacancy.

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