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Digital Verification Engineer Jobs in Arizona (NOW HIRING)

Intel

IP Design Verification Engineer

Phoenix, AZ

$141K - $200K/yr

Join Intel as a Mixed Signal Design Verification Engineer and play a critical role in shaping the ... Strong debugging skills in both analog and digital domains. * PCIe and/or UCIe protocols. * Test ...

Aptino

Hardware Validation/Verification Engineer

Phoenix, AZ · On-site

$122K - $161K/yr

Job Title: Hardware V&V Engineer Location: Phoenix, AZ (Onsite) Duration: 6-12 Months We are ... Experience using oscilloscopes, logic analyzers, power supplies, digital multimeters (DMMs), or ...

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How much do digital verification engineer jobs pay per year?

As of Jul 19, 2026, the average yearly pay for digital verification engineer in Arizona is $138,991.00, according to ZipRecruiter salary data. Most workers in this role earn between $126,700.00 and $154,700.00 per year, depending on experience, location, and employer.

What is a Digital Verification Engineer job?

A Digital Verification Engineer is responsible for ensuring the correctness of digital designs before manufacturing. They develop and implement testbenches using hardware description languages like SystemVerilog and methodologies like UVM. Their role involves writing test cases, debugging failures, and improving verification efficiency. The goal is to identify design issues early in the development cycle, reducing costly revisions.

What does a digital verification engineer do?

A digital verification engineer designs and develops test environments to ensure digital hardware and integrated circuits function correctly. They create test plans, write simulation testbenches using hardware description languages like VHDL or Verilog, and analyze simulation results to identify and fix design issues. Proficiency with verification tools and scripting languages is essential for this role.

What are the key skills and qualifications needed to thrive in the Digital Verification Engineer position, and why are they important?

To thrive as a Digital Verification Engineer, you need a solid background in digital design, computer engineering, and experience with verification methodologies, often supported by a Bachelor’s or Master’s degree in a related field. Proficiency with hardware description languages (such as Verilog, VHDL), simulation tools (like ModelSim, Questa), scripting languages (Python, Perl), and familiarity with standard verification methodologies (UVM, SystemVerilog) are typically required. Attention to detail, strong analytical thinking, and effective communication skills are crucial soft skills for collaborating with design teams and troubleshooting complex systems. These abilities ensure accurate verification outcomes, minimize design errors, and facilitate seamless teamwork in fast-paced semiconductor environments.

What engineers make $300,000 a year?

Senior engineers in specialized fields such as software engineering, electrical engineering, and systems engineering can earn $300,000 or more annually, especially with extensive experience, advanced skills, and working in high-demand industries like technology, finance, or aerospace. Roles often require advanced degrees, certifications, and leadership responsibilities.

Are verification engineers in demand?

Verification engineers are in high demand due to the increasing complexity of digital systems and the need for thorough testing to ensure reliability. Skills in hardware description languages like VHDL or Verilog, along with experience in simulation tools, enhance job prospects in this field.

What are some common daily responsibilities for a Digital Verification Engineer?

As a Digital Verification Engineer, your daily tasks typically include developing and maintaining testbenches, writing and executing test cases, and analyzing simulation results to identify potential design issues. You’ll work closely with design engineers to review specifications and debug hardware or firmware discrepancies, ensuring that the digital designs meet all functional and timing requirements. Collaborating within cross-functional teams and participating in regular code reviews are also standard parts of the workflow. This hands-on and collaborative environment helps accelerate product development and ensures high-quality deliverables.

What engineer makes $500,000 a year?

Highly experienced digital verification engineers working in senior or lead roles at large technology companies can earn salaries approaching or exceeding $500,000 annually, especially with bonuses and stock options. These roles typically require advanced skills in hardware design, verification tools, and extensive industry experience. Compensation varies based on location, company size, and individual expertise.
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Digital Verification Engineer jobs near you
Infographic showing various Digital Verification Engineer job openings in Arizona as of July 2026, with employment types broken down into 87% Full Time, 11% Part Time, and 2% Contract. Highlights an 89% Physical, 3% Hybrid, and 8% Remote job distribution, with an average salary of $138,991 per year, or $66.8 per hour.
Senior Staff Design Verification Engineer

Senior Staff Design Verification Engineer

Cirrus Logic

Chandler, AZ • On-site

$133K - $163K/yr

Full-time

Re-posted 6 days ago

Job description

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn't do it without our extraordinary workforce - and that's where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career!
We are seeking an experienced and innovative Design Verification Engineer to join a world-class silicon design verification team. This role partners closely with digital and analog designers, systems and applications engineers, firmware/software teams, and manufacturing test to deliver high-quality mixed-signal IC solutions. You will be responsible for end-to-end functional verification across block-level and chip-level designs, contributing to advanced verification methodologies and infrastructure.
This position offers exposure to multiple verification domains including UVM-based testbench development, formal verification, hardware emulation/acceleration, gate-level simulations, and software-driven verification in a highly collaborative and technically rigorous environment.
Responsibilities:
  • Develop comprehensive verification plans aligned with design and system requirements.
  • Perform functional verification of custom mixed-signal ASICs at block and chip level.
  • Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and assertions.
  • Create directed and constrained-random test suites to ensure robust functional coverage.
  • Implement, analyze, and drive functional and code coverage, including coverage closure.
  • Conduct failure analysis, regression triage, and debug, resolving functional and timing-related issues.
  • Run and debug gate-level simulations, including timing violations and back-annotation issues.
  • Develop and maintain digital and mixed-signal behavioral models to support verification.
  • Support verification flow and infrastructure development, including regressions and automation.
  • Collaborate cross-functionally with digital/analog design, systems, applications, firmware/software, and manufacturing test teams.
  • Contribute to both pre-silicon verification and post-silicon validation efforts.
  • Proactively improve verification methodologies, processes, and best practices.

Required Knowledge, Skills, and Experience:
  • Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field.
    • Bachelor's with 10+ years of relevant experience.
    • Master's with 8+ years of relevant experience.
    • PhD with 6+ years of relevant experience.
  • Significant industry experience in silicon design and/or ASIC verification.
  • Strong proficiency with HDLs: Verilog and/or VHDL.
  • Strong proficiency with HVLs: SystemVerilog with UVM (or OVM/AVM/Vera).
  • Solid understanding of digital design principles and system architecture.
  • Hands-on experience with:
    • Testbench architecture and stimulus generation.
    • Regression execution and debug.
    • Coverage analysis and closure.
  • Ability to work effectively in a cross-disciplinary, team-oriented environment.

Preferred Knowledge, Skills, and Experience:
  • Experience verifying mixed-signal ASICs in complex SoC environments.
  • Knowledge of signal processing concepts relevant to mixed-signal designs.
  • Experience with SystemVerilog Assertions (SVA).
  • Exposure to or hands-on experience with:
    • Formal verification
    • Hardware emulation or acceleration
    • Software-driven verification
  • Demonstrated ability to evaluate, debug, and improve verification flows and methodologies.

#LI-Hybrid
#LI-EK1
#HOTT
Export control restrictions based upon applicable laws and regulations would prohibit candidates who are nationals of certain embargoed countries from working in this position without Cirrus Logic first obtaining an export license. Candidates for this role must be able to access technical data without a requirement for an export license. We are unable to sponsor or obtain export licenses for this role.
Cirrus Logic strives to select the best qualified applicant for any opening. Different approaches, ideas and points of view are both valued and respected. Employment decisions are made on the basis of job-related criteria without regard to race, color, religion, sex, national origin, age, protected veteran or disabled status, genetic information, or any other classification protected by applicable law.

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