ASIC DFT Engineer
San Jose, CA · On-site
The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing ...
San Jose, CA · On-site
The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing ...
San Jose, CA · On-site
The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing ...
San Jose, CA · On-site
$179 - $286/hr
We are seeking an experienced Senior DFT Technical Manager to lead DFT design and implementation for advanced SoC products while serving as a key technical interface between customers and MediaTek ...
San Jose, CA · On-site
$179 - $286/hr
We are seeking an experienced Senior DFT Technical Manager to lead DFT design and implementation for advanced SoC products while serving as a key technical interface between customers and MediaTek ...
Principal DFT Engineer Broadcom's ASIC Product Division is seeking candidates for a DFT position at ourSan Jose, California,Development Center. The successful candidate will be responsible for ...
New
Principal DFT Engineer Broadcom's ASIC Product Division is seeking candidates for a DFT position at ourSan Jose, California,Development Center. The successful candidate will be responsible for ...
New
DFT Engineer Responsibilities * Define & document DFT requirements/Specifications for IP/Block and Chip level * Execute DFT Lint to identify scan DRC violations and resolution * Top level and hard ...
Quick apply
DFT Engineer Responsibilities * Define & document DFT requirements/Specifications for IP/Block and Chip level * Execute DFT Lint to identify scan DRC violations and resolution * Top level and hard ...
San Jose, CA · On-site
$159K - $296K/yr
The Principal DFT Engineer will work on cutting-edge ASIC implementation for the Network Infrastructure Optical Network group Responsibilities You will be working on DFT architecture and ...
San Jose, CA · On-site
$159K - $296K/yr
The Principal DFT Engineer will work on cutting-edge ASIC implementation for the Network Infrastructure Optical Network group Responsibilities You will be working on DFT architecture and ...
San Jose, CA · On-site
Role: Lead ASIC DFT Engineer Location: Remote Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to ...
Quick apply
San Jose, CA · On-site
Role: Lead ASIC DFT Engineer Location: Remote Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to ...
San Jose, CA · On-site
$141K - $226K/yr
The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing ...
San Jose, CA · On-site
$141K - $226K/yr
The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing ...
Mountain View, CA · On-site
$45K - $121K/yr
DFT Engineer City: Mountain View State/Province: California Posting Start Date: 7/21/26 Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company ...
Mountain View, CA · On-site
$45K - $121K/yr
DFT Engineer City: Mountain View State/Province: California Posting Start Date: 7/21/26 Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company ...
San Jose, CA · On-site
Title - Lead ASIC DFT Engineer Location - San Jose, CA - Open for Onsite/Remote (Should be in PST timings though) Visa- USC/GC Experience : 10+ years of hands-on experience in ASIC Design-for-Test ...
Quick apply
San Jose, CA · On-site
Title - Lead ASIC DFT Engineer Location - San Jose, CA - Open for Onsite/Remote (Should be in PST timings though) Visa- USC/GC Experience : 10+ years of hands-on experience in ASIC Design-for-Test ...
San Jose, CA · On-site
Title - Lead ASIC DFT Engineer Location - San Jose, CA. Visa- USC/GC Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ...
Quick apply
San Jose, CA · On-site
Title - Lead ASIC DFT Engineer Location - San Jose, CA. Visa- USC/GC Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ...
San Jose, CA · On-site
$149K - $213K/yr
The Altera DFT team is looking for a motivated DFT (Design for Testability) Design Engineer to join an industry-leading IC design organization. This is an opportunity to work on cutting-edge ...
San Jose, CA · On-site
$149K - $213K/yr
The Altera DFT team is looking for a motivated DFT (Design for Testability) Design Engineer to join an industry-leading IC design organization. This is an opportunity to work on cutting-edge ...
Santa Clara, CA · On-site
Position Overview We seek a DFT Application Engineer to provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies. This critical role ...
Santa Clara, CA · On-site
Position Overview We seek a DFT Application Engineer to provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies. This critical role ...
San Jose, CA · On-site
The Principal DFT Engineer will work on cutting-edge ASIC implementation for the Network Infrastructure Optical Network group You Have: * Bachelor's degree in computer science, Electrical Engineering ...
San Jose, CA · On-site
The Principal DFT Engineer will work on cutting-edge ASIC implementation for the Network Infrastructure Optical Network group You Have: * Bachelor's degree in computer science, Electrical Engineering ...
Saratoga, CA · On-site
$120 - $220/hr
We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...
Saratoga, CA · On-site
$120 - $220/hr
We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...
San Jose, CA · On-site
$149K - $213K/yr
The Altera DFT team is looking for a motivated DFT (Design for Testability) Design Engineer to join an industry-leading IC design organization. This is an opportunity to work on cutting-edge ...
San Jose, CA · On-site
$149K - $213K/yr
The Altera DFT team is looking for a motivated DFT (Design for Testability) Design Engineer to join an industry-leading IC design organization. This is an opportunity to work on cutting-edge ...
Saratoga, CA · On-site
$120K - $220K/yr
We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...
Saratoga, CA · On-site
$120K - $220K/yr
We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...
$120K - $220K/yr
We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...
Quick apply
$120K - $220K/yr
We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...
Saratoga, CA · On-site
$120K - $220K/yr
We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...
Saratoga, CA · On-site
$120K - $220K/yr
We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...
Santa Clara, CA · On-site
Perform hands-on DFT implementation , including: * MBIST and BISR insertion and integration * Boundary Scan (IEEE 1149.x) insertion * IJTAG (IEEE 1687) insertion and connectivity * Execute DFT ...
Santa Clara, CA · On-site
Perform hands-on DFT implementation , including: * MBIST and BISR insertion and integration * Boundary Scan (IEEE 1149.x) insertion * IJTAG (IEEE 1687) insertion and connectivity * Execute DFT ...
Develop DFT strategies for 2.5D/3D heterogeneous integration architectures: * Multi-die test access and coordination through silicon interposers * Through-Silicon Via (TSV) testing and ...
Develop DFT strategies for 2.5D/3D heterogeneous integration architectures: * Multi-die test access and coordination through silicon interposers * Through-Silicon Via (TSV) testing and ...
$68.6K - $70K
5% of jobs
$70K - $71.4K
9% of jobs
$71.4K - $72.8K
6% of jobs
$73.3K is the 25th percentile. Wages below this are outliers.
$72.8K - $74.2K
10% of jobs
$74.2K - $75.5K
10% of jobs
The median wage is $76.7K / yr.
$75.5K - $76.9K
10% of jobs
$76.9K - $78.3K
10% of jobs
$78.3K - $79.7K
10% of jobs
$80.2K is the 75th percentile. Wages above this are outliers.
$79.7K - $81.1K
6% of jobs
$81.1K - $82.5K
10% of jobs
$82.5K - $83.9K
10% of jobs
$68.6K
$77.1K
$83.9K
| Aspect | Dft | Draftsman |
|---|---|---|
| Required Credentials | Typically requires a diploma or certification in drafting or engineering | Often requires a diploma or technical training in drafting or architecture |
| Work Environment | Works in engineering, construction, or manufacturing settings | Works mainly in architectural or engineering offices |
| Industry Usage | Commonly used in engineering, manufacturing, and construction industries | Primarily used in architecture and civil engineering sectors |
| Job Focus | Designing and creating technical drawings for engineering projects | Preparing detailed architectural or structural drawings |
In summary, Dft and Draftsman roles share similar skills and work environments, often requiring technical diplomas. Dft typically refers to a broader engineering drafting role, while Draftsman is more focused on architectural drawings. Both are essential in their respective industries for translating concepts into technical plans.

Full-time
Medical, Dental, Vision, Retirement, PTO
Re-posted 9 days ago
8.7
Based on 23 frontline employees who took The Breakroom Quiz
19th of 157 rated electronics manufacturers
Please Note:
1. If you are a first time user, please create your candidatelogin account before you apply for a job. (Click Sign In > Create Account)
2. If you already have a Candidate Account, please Sign-In before you apply.
Job Description:Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at ourSan Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production.
The candidate would be required to work on various phases of SoC DFT related activities for APD's designs - DFT Architecture, test insertion and verification, pattern generation, coverage improvement, post silicon debug, and yield improvement to meet the product test metrics. It involves working with the Physical Design and STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.
Responsibilities:
Understanding Broadcom and customer DFT feature requirements, and DPPM goals and defining appropriate DFT specifications for the ASIC
Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
Pattern generation and verification at chip level, rapid bring-up at ATE and RMA support
Working closely with STA and DI Engineers design closure for test
Generating, verifying, and debugging test vectors before tape release
Validating and debugging test vectors on ATE during the silicon bring up phase
Assisting with silicon failure analysis, diagnostics, and yield improvement efforts
Interfacing with the customer, physical design and testengineering/manufacturingteams located globally
Working closely with I/P DFT engineers and other stakeholders
Debugging customer returned parts on the ATE
Innovating newer DFT solutions to solve testability problems in 3nm and beyond
Automating DFT and test vector generation flows
Skills/Experience:
Bachelors and 17+ years of related experience; or Masters degree and 15+ years of related experience
Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)
Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)
Logic BIST design and debug experience
Well-versed in ATPG vector generation, simulation, and debugging. (TetraMax, Fastscan)
Experience in Verilog coding, testbench generation and simulation
Memory BIST insertion and verification experience on embedded (SRAM, CAM, eDRAM, ROM)
Boundary scan verification and test vector generation. Should have good knowledge in IEEE1149.1 and IEEE1149.6
BasicknowledgeTest-STAand constraints
Strong background on IEE1687, IJTAG, ICL, and PDL
The ability to work in a multi-disciplined, cross-department environment
Solid knowledge in analog and digital circuit design, and device physics fundamentals
Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles
Excellent problem solving, debug, root cause analysis and communication skills
Strong understanding of statistical process control and data analysis techniques to drive silicon yield improvements and quality metrics
Project management capabilities to track and prioritize competing deliverables across cross-functional stakeholders including Test Engineering, Reliability, and Operations.
Experience working on ATE is a plus
Experience with Serdes, DDR, PCIE, ENET, CXL IOBIST verification, and silicon debug is a plus
Experience working on Tessent SSN is a plus
Compensation and Benefits
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Sourced by ZipRecruiter
Semiconductor and electronic component manufacturing
10,000+ Employees
Palo Alto, CA, US
1991