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Dft Jobs in California (NOW HIRING)

The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing ...

Principal DFT Engineer Broadcom's ASIC Product Division is seeking candidates for a DFT position at ourSan Jose, California,Development Center. The successful candidate will be responsible for ...

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Principal SoC DFT Engineer

San Jose, CA · On-site

$159K - $296K/yr

The Principal DFT Engineer will work on cutting-edge ASIC implementation for the Network Infrastructure Optical Network group Responsibilities You will be working on DFT architecture and ...

Role: Lead ASIC DFT Engineer Location: Remote Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to ...

ASIC DFT Engineer

San Jose, CA · On-site

$141K - $226K/yr

The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing ...

DFT Engineer

Mountain View, CA · On-site

$45K - $121K/yr

DFT Engineer City: Mountain View State/Province: California Posting Start Date: 7/21/26 Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company ...

DFT Design Engineer

San Jose, CA · On-site

$149K - $213K/yr

The Altera DFT team is looking for a motivated DFT (Design for Testability) Design Engineer to join an industry-leading IC design organization. This is an opportunity to work on cutting-edge ...

Position Overview We seek a DFT Application Engineer to provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies. This critical role ...

The Principal DFT Engineer will work on cutting-edge ASIC implementation for the Network Infrastructure Optical Network group You Have: * Bachelor's degree in computer science, Electrical Engineering ...

Senior DFT Engineer

Saratoga, CA · On-site

$120 - $220/hr

We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...

DFT Design Engineer

San Jose, CA · On-site

$149K - $213K/yr

The Altera DFT team is looking for a motivated DFT (Design for Testability) Design Engineer to join an industry-leading IC design organization. This is an opportunity to work on cutting-edge ...

Senior DFT Engineer

Saratoga, CA · On-site

$120K - $220K/yr

We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...

We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...

Senior DFT Engineer

Saratoga, CA · On-site

$120K - $220K/yr

We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...

Perform hands-on DFT implementation , including: * MBIST and BISR insertion and integration * Boundary Scan (IEEE 1149.x) insertion * IJTAG (IEEE 1687) insertion and connectivity * Execute DFT ...

Showing results 21-40

Dft information

See California salary details

$68.6K

$77.1K

$83.9K

How much do dft jobs pay per year?

As of Aug 12, 2026, the average yearly pay for dft in California is $77,077.00, according to ZipRecruiter salary data. Most workers in this role earn between $73,000.00 and $80,900.00 per year, depending on experience, location, and employer.

What is a DFT job?

A DFT job typically refers to a role involving Design for Testability, where professionals develop testing strategies and procedures to ensure the quality and reliability of electronic circuits and systems. It often requires knowledge of testing tools, circuit design, and industry standards, and may involve working with automated testing equipment. The position usually demands technical skills and attention to detail to identify and address potential manufacturing defects.

Is DFT engineering a good career?

DFT engineering, which involves designing and implementing design-for-testability features in integrated circuits, is a specialized field within electronics and semiconductor industries. It offers opportunities in chip design, testing, and quality assurance, often requiring knowledge of digital design, VLSI, and testing tools. The career can be stable and well-paying for those with relevant skills and certifications, with demand driven by advancements in semiconductor technology.

What is the difference between Dft vs Draftsman?

AspectDftDraftsman
Required CredentialsTypically requires a diploma or certification in drafting or engineeringOften requires a diploma or technical training in drafting or architecture
Work EnvironmentWorks in engineering, construction, or manufacturing settingsWorks mainly in architectural or engineering offices
Industry UsageCommonly used in engineering, manufacturing, and construction industriesPrimarily used in architecture and civil engineering sectors
Job FocusDesigning and creating technical drawings for engineering projectsPreparing detailed architectural or structural drawings

In summary, Dft and Draftsman roles share similar skills and work environments, often requiring technical diplomas. Dft typically refers to a broader engineering drafting role, while Draftsman is more focused on architectural drawings. Both are essential in their respective industries for translating concepts into technical plans.

What are the key skills and qualifications needed to thrive as a Design for Test (DFT) engineer?

To thrive as a Design for Test (DFT) Engineer, you need a solid background in digital design, VLSI concepts, and experience with ASIC/FPGA design, typically supported by a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys DFT Compiler, Mentor Tessent, and scripting languages like TCL or Python is essential, along with knowledge of test methodologies like scan insertion and ATPG. Strong problem-solving abilities, attention to detail, and effective communication skills help in debugging complex issues and collaborating across teams. These skills are vital for ensuring high-quality, testable hardware designs that meet production and reliability standards.

What are some common challenges faced by DFT engineers when collaborating with design and verification teams?

DFT engineers often encounter challenges ensuring their test structures integrate seamlessly with the main design and verification flows. Balancing test coverage with minimal impact on design performance requires ongoing communication and compromise. Additionally, DFT engineers must frequently align on methodologies and resolve conflicts between testability requirements and design constraints, making cross-functional teamwork essential for success.

What is a DFT engineer?

DFT engineers, or Design for Test engineers, are professionals in the semiconductor industry who specialize in designing and implementing testability features in integrated circuits (ICs) and systems-on-chip (SoCs). Their primary role is to ensure that chips can be efficiently and effectively tested for manufacturing defects after fabrication. This involves adding test structures, developing test methodologies, and working closely with design and verification teams to optimize test coverage and reduce the cost of testing. DFT engineers play a critical role in improving product quality and yield in chip manufacturing.

Is DFT a good place to work?

DFT, as a job title, typically refers to a role such as a Design for Test engineer or a similar technical position. The work environment and job satisfaction depend on the company, industry, and specific role, but these positions often require technical skills and attention to detail. Overall, the quality of the workplace varies and should be evaluated based on company culture, benefits, and career growth opportunities.
What are the most commonly searched types of Dft jobs in California? The most popular types of Dft jobs in California are:
What job categories do people searching Dft jobs in California look for? The top searched job categories for Dft jobs in California are:
What cities in California are hiring for Dft jobs? Cities in California with the most Dft job openings:
Infographic showing various Dft job openings in California as of July 2026, with employment types broken down into 78% Full Time, and 22% Contract. Highlights an 97% In-person, and 3% Remote job distribution, with an average salary of $77,077 per year, or $37.1 per hour.

ASIC DFT Engineer

Broadcom

San Jose, CA • On-site

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 9 days ago


Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz

19th of 157 rated electronics manufacturers


Job description

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Job Description:

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at ourSan Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production.

The candidate would be required to work on various phases of SoC DFT related activities for APD's designs - DFT Architecture, test insertion and verification, pattern generation, coverage improvement, post silicon debug, and yield improvement to meet the product test metrics. It involves working with the Physical Design and STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.

Responsibilities:

  • Understanding Broadcom and customer DFT feature requirements, and DPPM goals and defining appropriate DFT specifications for the ASIC

  • Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration

  • Pattern generation and verification at chip level, rapid bring-up at ATE and RMA support

  • Working closely with STA and DI Engineers design closure for test

  • Generating, verifying, and debugging test vectors before tape release

  • Validating and debugging test vectors on ATE during the silicon bring up phase

  • Assisting with silicon failure analysis, diagnostics, and yield improvement efforts

  • Interfacing with the customer, physical design and testengineering/manufacturingteams located globally

  • Working closely with I/P DFT engineers and other stakeholders

  • Debugging customer returned parts on the ATE

  • Innovating newer DFT solutions to solve testability problems in 3nm and beyond

  • Automating DFT and test vector generation flows

Skills/Experience:

  • Bachelors and 17+ years of related experience; or Masters degree and 15+ years of related experience

  • Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)

  • Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)

  • Logic BIST design and debug experience

  • Well-versed in ATPG vector generation, simulation, and debugging. (TetraMax, Fastscan)

  • Experience in Verilog coding, testbench generation and simulation

  • Memory BIST insertion and verification experience on embedded (SRAM, CAM, eDRAM, ROM)

  • Boundary scan verification and test vector generation. Should have good knowledge in IEEE1149.1 and IEEE1149.6

  • BasicknowledgeTest-STAand constraints

  • Strong background on IEE1687, IJTAG, ICL, and PDL

  • The ability to work in a multi-disciplined, cross-department environment

  • Solid knowledge in analog and digital circuit design, and device physics fundamentals

  • Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles

  • Excellent problem solving, debug, root cause analysis and communication skills

  • Strong understanding of statistical process control and data analysis techniques to drive silicon yield improvements and quality metrics

  • Project management capabilities to track and prioritize competing deliverables across cross-functional stakeholders including Test Engineering, Reliability, and Operations.

  • Experience working on ATE is a plus

  • Experience with Serdes, DDR, PCIE, ENET, CXL IOBIST verification, and silicon debug is a plus

  • Experience working on Tessent SSN is a plus


Compensation and Benefits


The annual base salary range for this position is USD 167,500.00 To USD 268,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.


Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.


Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.


If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.


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