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Temporary Asic Design Engineer Jobs in California

ASIC Design Engineer

San Francisco, CA · On-site

$130 - $210/hr

We're looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer. Ideal ...

ASIC Design Engineer

San Diego, CA · On-site

$99 - $148/hr

Qualcomm is seeking talented ASIC Design Engineers to join our growing SoC and ASIC Design organization. Successful candidates will have the opportunity to contribute across a variety of projects ...

ASIC Design Engineer

San Diego, CA · On-site

$99 - $148/hr

Qualcomm is seeking talented ASIC Design Engineers to join our growing SoC and ASIC Design organization. Successful candidates will have the opportunity to contribute across a variety of projects ...

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ASIC Design Engineer

Alameda, CA · On-site

$120 - $180/hr

The Role We're looking for an ASIC Design Engineer who wants to be involved in all aspects of design cycle: documentation, design, pre-silicon verification, and post-silicon validation. The team is ...

Posted today

Qualcomm is seeking talented ASIC Design Engineers to join our growing SoC and ASIC Design organization. Successful candidates will have the opportunity to contribute across a variety of projects ...

Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...

Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...

ASIC Design Engineer

Santa Clara, CA · On-site

$126.70 - $190.10/hr

Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience * Master's degree in Science, Engineering ...

We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of ...

ASIC Design Engineer

Santa Clara, CA · On-site

$126K - $190K/yr

OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related ...

Lead ASIC Design Engineer

San Jose, CA · On-site

$143.80 - $230/hr

Lead ASIC Design EngineerSkip to main content#Lead ASIC Design Engineer page is loaded## Lead ASIC Design EngineerApplylocations: USA-California-San Jose-1320 Ridder Park Drivetime type: Full ...

NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company ...

As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance ...

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Temporary Asic Design Engineer information

What is the difference between Temporary Asic Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Design EngineerTemporary FPGA Design Engineer
Required SkillsASIC architecture, digital design, verification, HDL (Verilog/VHDL)FPGA development, HDL (Verilog/VHDL), prototyping
Work EnvironmentSemiconductor companies, chip design labsPrototyping labs, FPGA manufacturing facilities
Industry UsageIntegrated circuit manufacturing, consumer electronicsPrototyping, testing, and development projects

Temporary Asic Design Engineers focus on designing and verifying ASIC chips, often working in semiconductor companies. Temporary FPGA Design Engineers work on FPGA prototyping and testing, typically in research or development labs. Both roles require HDL skills but differ in their focus on chip fabrication versus flexible prototyping.

Are temporary ASIC design engineers in demand?

Temporary ASIC design engineers are in demand due to the ongoing need for specialized hardware development in industries like telecommunications, consumer electronics, and data centers. Skills in hardware description languages such as VHDL or Verilog and experience with FPGA prototyping can enhance job prospects in this field.

How much does a Temporary ASIC Design Engineer make?

A Temporary ASIC Design Engineer typically earns between $40 and $70 per hour, depending on experience, location, and the complexity of the projects. Compensation may also include benefits such as flexible schedules and exposure to advanced design tools like Verilog and FPGA environments.

Is a temporary ASIC design engineer design difficult?

Designing as an ASIC design engineer can be complex due to the need for specialized knowledge in digital logic, hardware description languages, and verification tools. The difficulty varies based on project scope, experience, and familiarity with industry standards, but it generally requires strong technical skills and attention to detail.

What are the most commonly searched types of Asic Design Engineer jobs in California?

The most popular types of Asic Design Engineer jobs in California are:

What are popular job titles related to Temporary Asic Design Engineer jobs in California?

For Temporary Asic Design Engineer jobs in California, the most frequently searched job titles are:

What job categories do people searching Temporary Asic Design Engineer jobs in California look for?

The top searched job categories for Temporary Asic Design Engineer jobs in California are:

What cities in California are hiring for Temporary Asic Design Engineer jobs?

Cities in California with the most Temporary Asic Design Engineer job openings:

Infographic showing various Temporary Asic Design Engineer job openings in California as of August 2026, with employment types broken down into 83% Full Time, 12% Part Time, and 5% Contract. Highlights an 81% Physical, 5% Hybrid, and 14% Remote job distribution.

ASIC Design Engineer

San Francisco, CA • On-site

$130 - $210/hr

Other

Posted 14 days ago


Job description

We’re looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer.

Ideal Background:
  • Hands-on experience with multiple advanced node tapeouts
  • Ownership of ASIC design portion of at least one block in multiple advanced node tapeouts
  • Understanding of PPA improvement and what levers exist for each level of the stack
  • Ability to think creatively about methodology for fast design iterations
Nice to Have:
  • Hands-on experience with ASIC design process for large die (ideally reticle max) chips
  • Hands-on experience with ASIC design process for AI chips
  • Hands-on experience with multi-die/multi-chiplet/MCM designs
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