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Temporary Asic Design Engineer Jobs (NOW HIRING)

Piper Companies

Senior ASIC Design Engineer

Saratoga, CA · On-site

$250K - $290K/yr

Piper Companies is looking for a Senior ASIC Design Engineer to join a cutting-edge AI networking company onsite in Saratoga, CA Monday - Friday , to help define and build the next generation of high ...

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Fusion408

Principal ASIC Design Engineer

Carlsbad, CA · On-site

Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...

Credo

Principal ASIC Design Engineer

San Jose, CA · On-site

$180K - $210K/yr

About the Role As a Principal ASIC Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will ...

ServerLogic

Senior ASIC Design Engineer

Beaverton, OR · On-site

Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a block of an ASIC and write a microarchitecture specification (MAS) for the block * Collaborate with ...

Qualcomm

ASIC Design Engineer

Santa Clara, CA · On-site

$126K - $190K/yr

OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related ...

Atom Computing

Principal ASIC Design Engineer

Boulder, CO · On-site

$180K - $220K/yr

... engineering, specifically in ASIC/SoC environments. Qualifications * Have gone through 2 or more complete ASIC design cycles. * Experience porting designs from FPGA prototypes to ASICs * Proficiency ...

Cisco

ASIC Design Engineer

San Jose, CA · On-site

$165K - $241K/yr

Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources ... Design and implement high-frequency, high-performance RTL in Verilog / System Verilog, meeting ...

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How much do temporary asic design engineer jobs pay per year?

As of Jun 5, 2026, the average yearly pay for temporary asic design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is the difference between Temporary Asic Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Design EngineerTemporary FPGA Design Engineer
Required SkillsASIC architecture, digital design, verification, HDL (Verilog/VHDL)FPGA development, HDL (Verilog/VHDL), prototyping
Work EnvironmentSemiconductor companies, chip design labsPrototyping labs, FPGA manufacturing facilities
Industry UsageIntegrated circuit manufacturing, consumer electronicsPrototyping, testing, and development projects

Temporary Asic Design Engineers focus on designing and verifying ASIC chips, often working in semiconductor companies. Temporary FPGA Design Engineers work on FPGA prototyping and testing, typically in research or development labs. Both roles require HDL skills but differ in their focus on chip fabrication versus flexible prototyping.

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Temporary Asic Design Engineer jobs near you
Infographic showing various Temporary Asic Design Engineer job openings in the United States as of May 2026, with employment types broken down into 1% As Needed, 56% Full Time, 38% Part Time, and 5% Contract. Highlights an 86% Physical, 9% Hybrid, and 5% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.
Senior ASIC Design Engineer

Senior ASIC Design Engineer

Piper Companies

Saratoga, CA • On-site

$250K - $290K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 2 days ago

Job description

Piper Companies is looking for a Senior ASIC Design Engineer to join a cutting-edge AI networking company onsite in Saratoga, CA Monday - Friday , to help define and build the next generation of high-performance networking ASICs. The ideal Senior ASIC Design Engineer will bridge the gap between high-level system design and ASIC implementation to help shape the future of data communication.
Responsibilities for the Senior ASIC Design Engineer:

  • Work with the CTO and engineering teams to translate system-level requirements into detailed ASIC architecture.
  • Lead architectural modeling and analysis to ensure optimal throughput, latency, and power efficiency.
  • Collaborate with RTL, Verification, Physical Design, and Firmware teams to ensure seamless implementation.
  • Drive integration of high-speed I/O and third-party IPs into the ASIC design.
Qualifications for Senior ASIC Design Engineer:
  • 10+ years of experience as an Chip Architect, preferably in networking or high-performance computing (Routers, Switches, GPU, CPU, Data Center, etc)
  • Must be eligible to work in the United States and obtain and maintain an Active U.S. Government Secret Clearance.
  • Deep understanding of networking protocols (Ethernet, TCP/IP, VLAN, MPLS, RoCE) and their hardware implications.
  • Proven experience in architecture design, performance modeling, and architectural trade-offs.
  • Familiarity with high-speed I/O (PCIe Gen5/Gen6, SerDes) and software control plane interfaces.
  • Experience across the full ASIC development lifecycle-from concept to silicon validation.
  • Master's degree in Electrical Engineering or related field required.
Compensation/Benefits for the Senior ASIC Design Engineer:
  • Salary Range: $250,000 - $290,000 annually (based on experience and qualifications)
  • Comprehensive Benefits: Medical, Dental, Vision, 401K, PTO, Sick Leave (if required by law), and Holidays
This job opens for applications on 6/1/2026. Applications for this job will be accepted for at least 30 days from the posting date. Keywords: ASIC, ASIC Architect, Networking ASIC, AI Networking, Design, Microarchitecture, Performance Modeling, PCIe, SerDes, Ethernet, TCP/IP, RoCE, High-Speed Datapath, Silicon Validation, System-on-Chip, SoC Architecture, Hardware Design, IP Integration, Physical Design, Firmware Interface, Chip Architect, DPU, CPU, SOC #LI-BR1 #LI-ON SITE

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