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Dft Intern Jobs in California (NOW HIRING)

Etched

DFT Intern

San Jose, CA · On-site

$17.50 - $23.50/hr

Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams ...

Etched

DFT Intern

San Jose, CA · On-site

$17.50 - $23.50/hr

Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams ...

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Dft Intern information

What are the key skills and qualifications needed to thrive as a DFT intern, and why are they important?

To thrive as a DFT Intern, you need a solid understanding of digital logic design, test methodologies, and a background in electrical engineering or computer engineering. Familiarity with hardware description languages (like Verilog or VHDL), EDA tools such as Synopsys or Cadence, and knowledge of scan insertion or ATPG techniques is typically required. Strong analytical skills, attention to detail, and effective communication help you collaborate with design teams and troubleshoot complex issues. These skills ensure you can efficiently contribute to creating testable, reliable integrated circuits, which is vital for product quality and manufacturability.

What is the difference between Dft Intern vs Mechanical Engineering Intern?

AspectDft InternMechanical Engineering Intern
Required CredentialsTypically pursuing or holding a degree in design, engineering, or related fieldsUsually enrolled in or holding a degree in mechanical engineering or related disciplines
Work EnvironmentDesign studios, CAD labs, or engineering departmentsManufacturing plants, engineering offices, or R&D labs
Employer & Industry UsageDesign firms, engineering consultancies, manufacturing companiesAutomotive, aerospace, manufacturing industries
Common Search & ComparisonOften compared with Mechanical Engineering Intern due to overlapping skills and industry

The Dft Intern and Mechanical Engineering Intern roles share similarities in educational background and industry usage. However, Dft Interns focus more on design and drafting tasks, while Mechanical Engineering Interns are involved in broader engineering projects. Both positions provide valuable industry experience, but their specific responsibilities and work environments differ based on their focus areas.

What types of projects or tasks can a DFT intern expect to be assigned during their internship?

As a DFT (Design for Test) Intern, you can expect to work on a variety of tasks such as developing and validating test logic, assisting with scan insertion, running simulations to verify test coverage, and supporting the implementation of automated test patterns. Interns often collaborate closely with senior DFT engineers, RTL designers, and verification teams to optimize testability and fault coverage of integrated circuits. These projects provide practical exposure to industry-standard tools and methodologies, making it an excellent opportunity to build relevant skills for a future career in semiconductor design or verification.

What is a DFT intern?

A DFT Intern is a student or entry-level professional who assists in the Design for Testability (DFT) process within semiconductor or hardware design teams. Their primary responsibilities include supporting the implementation and verification of DFT techniques such as scan insertion, boundary scan, and built-in self-test (BIST) in integrated circuits. DFT Interns work closely with design and verification engineers to ensure chips are testable and meet quality standards. The role is ideal for those studying electrical engineering or computer engineering with an interest in VLSI and hardware design.

What are the most commonly searched types of Dft jobs in California?

The most popular types of Dft jobs in California are:

What cities in California are hiring for Dft Intern jobs?

Cities in California with the most Dft Intern job openings:

Dft Intern jobs near you
Infographic showing various Dft Intern job openings in California as of August 2026, with employment types broken down into 100% Internship. Highlights an 100% In-person job distribution.

DFT Intern

Etched

San Jose, CA • On-site

$17.50 - $23.50/hr

Other

Re-posted 4 days ago

Job description

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams, contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations), and develop flows for various ATPG fault models. You do not necessarily need prior DFT experience; just the ability to learn quickly in a fast-paced, high-autonomy environment. We are looking for Summer '26, Fall '26, Spring '27, and Summer '27 interns.

You may be a good fit if you have

  • Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.

  • Familiarity with a hardware description language (Verilog or SystemVerilog)

  • Exposure to ASIC or SoC design concepts

  • Familiarity with digital logic design fundamentals

  • Familiarity with standard ASIC design flow steps (synthesis, STA, DFT)

  • Familiarity with scripting in Python, Tcl, or another language

  • Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience with

  • Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression

  • Experience with Tessent or similar DFT tooling

  • Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)

  • Exposure to DFT flow automation or regression infrastructure

  • Familiarity with clocking and reset schemes

We encourage you to apply even if you do not believe you meet every single qualification.

Program details

  • 12-week paid internship

  • Generous housing support for those relocating

  • Daily lunch and dinner in our office

  • Based at our office in San Jose, CA

  • Direct mentorship from industry leaders and world-class engineers

  • Opportunity to work on one of the most important problems of our time

For any questions, contact internships@etched.com.

How we’re different

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.

 

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.