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Dft Engineer Jobs in California (NOW HIRING)

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Palo Alto, CA · On-site

$175K - $280K/yr

Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're ...

Socket.dev

DFT Engineer, Google Cloud

Sunnyvale, CA · On-site

$138 - $197/hr

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 3 years of experience in DFT architecture, implementation ...

New

Nvidia Corporation

Senior DFT Engineer

Santa Clara, CA · On-site

$122K - $168K/yr

At NVIDIA, our Senior DFT Engineers lead the way in silicon test innovation, ensuring flawless execution and outstanding quality in our next-generation silicon platforms. This is an outstanding ...

Quest Global

Lead DFT Engineer

San Jose, CA · On-site

$150K - $180K/yr

DFT DRC (spyglass) Company Description Who We Are: Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing ...

DensityAI

Design for Test (DFT) Engineer

Mountain View, CA · On-site

$300K - $350K/yr

About the Role We are seeking an experienced Design-for-Test (DFT) Engineer to join our silicon engineering team and help stand up the DFT function alongside the architecture and physical-design (PD ...

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Palo Alto, CA · On-site

$175K - $280K/yr

Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're ...

Nvidia

Senior DFT Engineer

Santa Clara, CA · Hybrid

$122K - $168K/yr

NVIDIA's DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire Scan Test Lifecycle, we drive innovation for the most advanced silicon in ...

Micron

Principal DFT Engineer, HBM

Folsom, CA · On-site

$146K - $309K/yr

As a Principal SoC DFT Engineer within the Heterogeneous Integration Group (HIG), you will be responsible for the DFT architecture, implementation, and signoff of complex HBM base-die System-on-Chip ...

Google Inc.

SoC DFT Engineer, Cloud

Sunnyvale, CA · On-site

$163 - $237/hr

* Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. * 5 years of experience in DFT architecture ...

Cisco

ASIC DFT Engineer

San Jose, CA · On-site

$152K - $219K/yr

Prior experience working in the latest innovative trends in DFT, test and silicon engineering. * Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary ...

DensityAI

Design for Test (DFT) Engineer

Mountain View, CA · On-site

$300K - $350K/yr

About the Role We are seeking an experienced Design-for-Test (DFT) Engineer to join our silicon engineering team and help stand up the DFT function alongside the architecture and physical-design (PD ...

Eridu AI

DFT Engineer

Saratoga, CA · On-site

$195K - $250K/yr

The company is in execution mode and has a world-class engineering team with decades of experience ... Define the DFT architecture of a multi-chip system SOC. involving all aspects of test design ...

Nvidia Corporation

Senior DFT Engineer

Santa Clara, CA · On-site

$122K - $168K/yr

NVIDIA's DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire Scan Test Lifecycle, we drive innovation for the most advanced silicon in ...

Google

SoC DFT Engineer, Cloud

Sunnyvale, CA · On-site

$144K - $191K/yr

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. * 5 years of experience in DFT architecture ...

Google

DFT Engineer, Google Cloud

Sunnyvale, CA · On-site

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 3 years of experience in DFT architecture, implementation ...

Micron Technology

Principal DFT Engineer, HBM

Folsom, CA · On-site

$146K - $309K/yr

As a Principal SoC DFT Engineer within the Heterogeneous Integration Group (HIG), you will be responsible for the DFT architecture, implementation, and signoff of complex HBM base-die System-on-Chip ...

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All JobsDft Engineer JobsDft Engineer Jobs in California

Dft Engineer information

See California salary details

$72K

$127.8K

$245.7K

How much do dft engineer jobs pay per year?

As of Aug 21, 2026, the average yearly pay for dft engineer in California is $127,815.00, according to ZipRecruiter salary data. Most workers in this role earn between $101,700.00 and $132,700.00 per year, depending on experience, location, and employer.

What is a DFT engineer?

DFT Engineers, or Design for Test Engineers, are professionals who specialize in designing and implementing test structures and methodologies within integrated circuits (ICs) to ensure their testability and reliability during manufacturing. Their work enables efficient detection and diagnosis of faults in chips, helping to improve yield and reduce production costs. DFT Engineers collaborate closely with design, verification, and manufacturing teams to integrate features such as scan chains, built-in self-test (BIST), and boundary scan into chip designs. Their expertise is crucial for modern semiconductor development, especially as chips become increasingly complex.

What are the key skills and qualifications needed to thrive as a DFT engineer?

To thrive as a DFT (Design for Test) Engineer, you need a solid background in electrical engineering, digital design, and ASIC/FPGA development, often supported by a relevant degree. Familiarity with test methodologies, scan insertion tools (such as Synopsys DFT Compiler or Mentor Tessent), and scripting languages like Perl or Python is typically required. Strong problem-solving skills, attention to detail, and effective communication help DFT Engineers collaborate with design and verification teams to resolve complex testability challenges. These competencies are essential to ensure high-quality, testable silicon designs that minimize defects and streamline manufacturing processes.

What are some common challenges faced by DFT engineers during the silicon validation phase, and how can these be addressed?

DFT Engineers often encounter challenges during the silicon validation phase, such as discrepancies between simulation results and actual silicon behavior, limited access to internal nodes, and diagnosing scan chain failures. These issues can be addressed by thorough pre-silicon verification, incorporating robust test points, and leveraging advanced diagnostic tools and methodologies. Effective collaboration with design and validation teams is also crucial to quickly resolve issues and implement necessary design changes, ensuring high test coverage and product reliability.

What is the difference between Dft Engineer vs Test Engineer?

AspectDft EngineerTest Engineer
Required CredentialsBachelor's in Electronics, Electrical, or related fields; certifications in DFT techniquesBachelor's in Electronics, Electrical, Computer Science; certifications in testing methodologies
Work EnvironmentDesign and implementation of DFT strategies during IC developmentTesting, validation, and debugging of electronic products and systems
Employer & Industry UsageSemiconductor companies, IC design firmsConsumer electronics, automotive, telecommunications industries

While both Dft Engineers and Test Engineers work in electronics and semiconductor industries, Dft Engineers focus on designing testability features during chip development, whereas Test Engineers execute testing and validation of finished products. Their roles complement each other, but their daily tasks and expertise areas differ significantly.

Is DFT engineering in demand?

DFT (Design for Test) engineering is in demand within the semiconductor and integrated circuit industries, as companies seek to improve chip testability and reduce manufacturing costs. Skills in digital design, verification, and familiarity with EDA tools are valuable, and demand is driven by ongoing advancements in electronics and increasing complexity of chips.

What are the most commonly searched types of Dft Engineer jobs in California?

The most popular types of Dft Engineer jobs in California are:

What are popular job titles related to Dft Engineer jobs in California?

For Dft Engineer jobs in California, the most frequently searched job titles are:

What job categories do people searching Dft Engineer jobs in California look for?

The top searched job categories for Dft Engineer jobs in California are:

What cities in California are hiring for Dft Engineer jobs?

Cities in California with the most Dft Engineer job openings:

Dft Engineer jobs near you
Infographic showing various Dft Engineer job openings in California as of August 2026, with employment types broken down into 95% Full Time, 2% Part Time, and 3% Contract. Highlights an 85% Physical, 6% Hybrid, and 9% Remote job distribution, with an average salary of $127,815 per year, or $61.4 per hour.

Sr. ASIC DFT Engineer (Silicon)

SpaceX

Palo Alto, CA • On-site

$175K - $280K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 21 days ago

SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 149 frontline employees who took The Breakroom Quiz

17th of 72 rated aerospace companies

Job description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR. ASIC DFT ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering and ASIC implementation). In this role, you will be developing next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
  • Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools
  • Integration and verification of Design for Test (DFT) IPs and fabrics within Subsystems
  • Set up and run Automatic Test Pattern Generation (ATPG) tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows.
  • Run and debug non-timing and SDF annotated gate-level simulations
  • Create and validate DFT patterns for post-silicon bringup and also help with ATE debug through all cycles of silicon characterization
  • Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C++

BASIC QUALIFICATIONS:
  • Bachelor's degree in electrical engineering, computer engineering, or physics
  • 5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing

PREFERRED SKILLS AND EXPERIENCE:
  • Master's or PhD in electrical engineering, computer engineering, physics, or related engineering field
  • Extensive experience in post-silicon bringup, including silicon debug, failure analysis, and yield optimization on complex SoCs or ASICs
  • Hands-on experience with Automated Test Equipment (ATE) platforms (e.g., Teradyne, Advantest) for high-volume manufacturing test development and debug
  • Experience collaborating with cross-functional teams (e.g., design, verification, and manufacturing) to ensure DFT features meet production requirements, utilizing Siemens Tessent workflows
  • Knowledge of industry standards for testability (e.g., IEEE 1500, 1687) and experience with low-power DFT techniques using Siemens Tessent
  • Experience with In-System Test (IST), boundary scan (IEEE 1149.1), functional testing in embedded systems, or board-level diagnostics, preferably using Siemens Tessent tools
  • Hands-on experience with Tessent Streaming Scan Network
  • Experience with cell-aware fault models in ATPG
  • Excellent problem-solving skills, with the ability to analyze complex test failures and implement corrective actions
  • Strong communication skills for documenting test strategies, reporting results, and presenting to stakeholders
  • Ability to work in a fast-paced environment, handling multiple projects and adapting to evolving technology nodes (e.g., 7nm and below)

ADDITIONAL REQUIREMENTS:
  • Ability to work extended hours and weekends as needed to meet critical milestones

COMPENSATION AND BENEFITS:
Pay Range:
DFT Engineer/Senior: $175,000.00 - $280,000.00/per year
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.
ITAR REQUIREMENTS:
    Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to

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Industry

Aerospace product and parts manufacturing, data services, guided missile and space vehicle manufacturing and satellite telecommunications

Company size

1,001 - 5,000 Employees

Headquarters location

Hawthorne, CA, US

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