Sr. ASIC Layout Design Engineer
$113K - $151K/yr
We are seeking an experienced Senior Analog/Mixed-Signal Layout Design Engineer to help develop the next generation of high-performance focal-plane array readout integrated circuits (ROICs). These ...
$113K - $151K/yr
We are seeking an experienced Senior Analog/Mixed-Signal Layout Design Engineer to help develop the next generation of high-performance focal-plane array readout integrated circuits (ROICs). These ...
$113K - $151K/yr
We are seeking an experienced Senior Analog/Mixed-Signal Layout Design Engineer to help develop the next generation of high-performance focal-plane array readout integrated circuits (ROICs). These ...
Goleta, CA · On-site
$113K - $151K/yr
We are seeking an experienced Senior Analog/Mixed-Signal Layout Design Engineer to help develop the next generation of high-performance focal-plane array readout integrated circuits (ROICs). These ...
Goleta, CA · On-site
$113K - $151K/yr
We are seeking an experienced Senior Analog/Mixed-Signal Layout Design Engineer to help develop the next generation of high-performance focal-plane array readout integrated circuits (ROICs). These ...
You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. * Job duties will include floor planning, custom layout and verifying against design rules and ...
You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. * Job duties will include floor planning, custom layout and verifying against design rules and ...
You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. * Job duties will include floor planning, custom layout and verifying against design rules and ...
You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. * Job duties will include floor planning, custom layout and verifying against design rules and ...
Job Title: "Senior Layout Design Engineer" Location: San Jose, CA (Onsite, 5 days a week) Duration: Long Term Description Client is looking for a talent that has strong background and hands-on ...
Job Title: "Senior Layout Design Engineer" Location: San Jose, CA (Onsite, 5 days a week) Duration: Long Term Description Client is looking for a talent that has strong background and hands-on ...
Santa Clara, CA · On-site
$237K/yr
Analog Layout Design Engineer Job Location: Santa Clara, CA (Onsite for 5 days a week) Job Type: Long-term contract Duration: 12 months Minimum Qualifications * The ideal candidate should have a ...
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Santa Clara, CA · On-site
$237K/yr
Analog Layout Design Engineer Job Location: Santa Clara, CA (Onsite for 5 days a week) Job Type: Long-term contract Duration: 12 months Minimum Qualifications * The ideal candidate should have a ...
Analog Layout Design Engineer Job location: Santa Clara, CA, 95054 Job Duration: 3 Months, Contract to Hire * Experience with layout of cutting-edge high-performance, high-speed CMOS integrated ...
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Analog Layout Design Engineer Job location: Santa Clara, CA, 95054 Job Duration: 3 Months, Contract to Hire * Experience with layout of cutting-edge high-performance, high-speed CMOS integrated ...
$117K - $195K/yr
Keysight Technologies has an opening for an Analog Layout Engineer in its ASIC/MMIC Design Center in Colorado Springs. This specific position is to support a team of ASIC/MMIC designers by laying out ...
$117K - $195K/yr
Keysight Technologies has an opening for an Analog Layout Engineer in its ASIC/MMIC Design Center in Colorado Springs. This specific position is to support a team of ASIC/MMIC designers by laying out ...
San Jose, CA · On-site
Perform post-layout Hspice simulation to characterize the designed circuit. * Assist with test ... Master's degree in Electrical Engineering/Computer Science. * 6 months experience as an ASIC Design ...
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San Jose, CA · On-site
Perform post-layout Hspice simulation to characterize the designed circuit. * Assist with test ... Master's degree in Electrical Engineering/Computer Science. * 6 months experience as an ASIC Design ...
San Jose, CA · On-site
Perform post-layout Hspice simulation to characterize the designed circuit. * Assist with test ... Masters degree in Electrical Engineering/Computer Science. * 6 months experience as an ASIC Design ...
Quick apply
San Jose, CA · On-site
Perform post-layout Hspice simulation to characterize the designed circuit. * Assist with test ... Masters degree in Electrical Engineering/Computer Science. * 6 months experience as an ASIC Design ...
Santa Clara, CA · On-site
$144.60 - $263.80/hr
Exceed engineering specifications and expectations. * Use advanced CAD tools, mask design knowledge to layout corrections and robust physical design representation of circuits. Minimum Qualifications
Santa Clara, CA · On-site
$144.60 - $263.80/hr
Exceed engineering specifications and expectations. * Use advanced CAD tools, mask design knowledge to layout corrections and robust physical design representation of circuits. Minimum Qualifications
Santa Clara, CA · On-site
$182K - $273K/yr
Coach and train junior engineers to foster skill development within the team. About you: * Minimum of 8 years' experience in custom layout design. * Current hands-on experience with 3nm technology is ...
Santa Clara, CA · On-site
$182K - $273K/yr
Coach and train junior engineers to foster skill development within the team. About you: * Minimum of 8 years' experience in custom layout design. * Current hands-on experience with 3nm technology is ...
We are seeking a high-performing PCB Layout Hardware Design Engineer interested in leading the in-house development of GM electronics design. You will be responsible for the electrical design ...
We are seeking a high-performing PCB Layout Hardware Design Engineer interested in leading the in-house development of GM electronics design. You will be responsible for the electrical design ...
San Jose, CA · On-site +1
$239K/yr
Senior to Principal High-Speed Analog Layout Design Engineer roles Locations : Irvine, CA or San Jose, CA or remote About the Role Celero Communication Inc. is an exciting and fast-growing start-up ...
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San Jose, CA · On-site +1
$239K/yr
Senior to Principal High-Speed Analog Layout Design Engineer roles Locations : Irvine, CA or San Jose, CA or remote About the Role Celero Communication Inc. is an exciting and fast-growing start-up ...
San Francisco, CA · On-site
$130 - $210/hr
We're looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer. Ideal ...
New
San Francisco, CA · On-site
$130 - $210/hr
We're looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer. Ideal ...
New
Irvine, CA · On-site +1
$217K/yr
Senior to Principal High-Speed Analog Layout Design Engineer roles Locations : Irvine, CA or San Jose, CA or remote About the Role Celero Communication Inc. is an exciting and fast-growing start-up ...
Quick apply
Irvine, CA · On-site +1
$217K/yr
Senior to Principal High-Speed Analog Layout Design Engineer roles Locations : Irvine, CA or San Jose, CA or remote About the Role Celero Communication Inc. is an exciting and fast-growing start-up ...
Santa Clara, CA · On-site
$156K - $160K/yr
... Image Sensor such as asic_pixel array, column-amplifier, switch capacitor, comparator, ramp ... Collaborate with layout engineer on whole chip layout integration and improvement by Cadence ...
Santa Clara, CA · On-site
$156K - $160K/yr
... Image Sensor such as asic_pixel array, column-amplifier, switch capacitor, comparator, ramp ... Collaborate with layout engineer on whole chip layout integration and improvement by Cadence ...
San Diego, CA · On-site
Qualcomm is seeking talented ASIC Design Engineers to join our growing SoC and ASIC Design organization. Successful candidates will have the opportunity to contribute across a variety of projects ...
New
San Diego, CA · On-site
Qualcomm is seeking talented ASIC Design Engineers to join our growing SoC and ASIC Design organization. Successful candidates will have the opportunity to contribute across a variety of projects ...
New
We are looking for a Senior Photonic Layout Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling high-speed mixed-signal & Silicon Photonic ...
We are looking for a Senior Photonic Layout Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling high-speed mixed-signal & Silicon Photonic ...
Santa Clara, CA · On-site
$156K - $160K/yr
... Image Sensor such as asic_pixel array, column-amplifier, switch capacitor, comparator, ramp ... Collaborate with layout engineer on whole chip layout integration and improvement by Cadence ...
Santa Clara, CA · On-site
$156K - $160K/yr
... Image Sensor such as asic_pixel array, column-amplifier, switch capacitor, comparator, ramp ... Collaborate with layout engineer on whole chip layout integration and improvement by Cadence ...
| Aspect | Asic Layout Design Engineer | Digital IC Design Engineer |
|---|---|---|
| Primary Focus | Physical layout and placement of ASIC components | Logical design and architecture of digital circuits |
| Skills Required | EDA tools, layout optimization, fabrication process knowledge | HDL coding, simulation, digital logic design |
| Work Environment | ASIC design teams, fabrication facilities | Design houses, semiconductor companies |
| Certifications | Typically none specific, but familiarity with industry standards | HDL certifications, digital design courses |
While both roles are integral to ASIC development, the Asic Layout Design Engineer focuses on the physical implementation of circuits, ensuring manufacturability and performance. In contrast, the Digital IC Design Engineer concentrates on the logical design and verification of digital circuits. Both roles require knowledge of digital design principles, but their daily tasks and skill sets differ significantly.

8.3
Based on 49 frontline employees who took The Breakroom Quiz
41st of 157 rated electronics manufacturers
Be visionary
Teledyne Technologies Incorporated provides enabling technologies for industrial growth markets that require advanced technology and high reliability. These markets include aerospace and defense, factory automation, air and water quality environmental monitoring, electronics design and development, oceanographic research, deepwater oil and gas exploration and production, medical imaging and pharmaceutical research.
We are looking for individuals who thrive on making an impact and want the excitement of being on a team that wins.
Job Description
Job Summary: We are seeking an experienced Senior Analog/Mixed-Signal Layout Design Engineer to help develop the next generation of high-performance focal-plane array readout integrated circuits (ROICs). These chips form the heart of our infrared detectors, sensors, and cameras-used in applications ranging from firefighting and security to scientific research and government contracts.
As part of our close-knit team, you will play a key role in producing analog and mixed-signal circuit layouts by preparing multi-dimensional, detailed drawings of the semiconductor devices from schematics provided by design engineering. You will collaborate closely with analog and digital circuit designers, ensuring precision in signal integrity, parasitic coupling, and matched transistor pairs. From initial design discussions to final tape-out, your expertise will help shape industry-leading imaging technology.
Must be US Citizen or PERM Resident
Primary Duties & Responsibilities:
What You Bring:
Salary Range:
$113,600.00-$151,400.000The anticipated salary range listed for this role is only an estimate. Actual compensation for successful candidates is carefully determined based on several factors including, but not limited to, location, local regulations (such as minimum wage), education/training, work experience, key skills, and type of position.
Teledyne and all of our employees are committed to conducting business with the highest ethical standards. We require all employees to comply with all applicable laws, regulations, rules and regulatory orders. Our reputation for honesty, integrity and high ethics is as important to us as our reputation for making innovative sensing solutions.
Teledyne is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability or veteran status, age, or any other characteristic or non-merit based factor made unlawful by federal, state, or local laws.
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Electrical equipment, appliance, and component manufacturing
5,001 - 10,000 Employees
Thousand Oaks, CA, US
1960