You'll work multi-functional with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. * Take part in floor planning, custom layout and verifying against design ...
You'll work multi-functional with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. * Take part in floor planning, custom layout and verifying against design ...
... Design engineers with solid ASIC design experience in San Diego, CA. This is a high-level, high ... closure, Layout, and thorough Silicon Testing. Candidates will be exposed and involved in ...
... Design engineers with solid ASIC design experience in San Diego, CA. This is a high-level, high ... closure, Layout, and thorough Silicon Testing. Candidates will be exposed and involved in ...
Senior ASIC Design Engineer with Security Clearance
Saratoga, CA ยท On-site
$250K - $290K/yr
Piper Companies is looking for a Senior ASIC Design Engineer to join a cutting-edge AI networking company onsite in Saratoga, CA Monday - Friday , to help define and build the next generation of high ...
Senior ASIC Design Engineer with Security Clearance
Saratoga, CA ยท On-site
$250K - $290K/yr
Piper Companies is looking for a Senior ASIC Design Engineer to join a cutting-edge AI networking company onsite in Saratoga, CA Monday - Friday , to help define and build the next generation of high ...
ASIC RTL/SoC Design Engineer
Fremont, CA ยท On-site
Experience with pre-layout simulation and post-layout simulation * Understanding of the design flow ... FPGA/ASIC design of image processing systems * Working knowledge of SoC architecture such as CPU ...
ASIC RTL/SoC Design Engineer
Fremont, CA ยท On-site
Experience with pre-layout simulation and post-layout simulation * Understanding of the design flow ... FPGA/ASIC design of image processing systems * Working knowledge of SoC architecture such as CPU ...
ASIC Design Engineer In this role, you will be part of the core team designing our next-generation AI compute engines. You will go beyond high-level RTL, diving into the fundamental hardware ...
ASIC Design Engineer In this role, you will be part of the core team designing our next-generation AI compute engines. You will go beyond high-level RTL, diving into the fundamental hardware ...
ASIC/RTL Design Engineer Location: San Jose, CA Duration : 12 months plus JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA ...
ASIC/RTL Design Engineer Location: San Jose, CA Duration : 12 months plus JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA ...
Experience with pre-layout simulation and post-layout simulation * Understanding of the design flow ... FPGA/ASIC design of image processing systems * Working knowledge of SoC architecture such as CPU ...
Experience with pre-layout simulation and post-layout simulation * Understanding of the design flow ... FPGA/ASIC design of image processing systems * Working knowledge of SoC architecture such as CPU ...
PCB Design Engineer
Irvine, CA ยท On-site
PCB Design Engineer Location : Irvine, California, 100% onsite Position type: Contract Visa: US ... Perform high-speed and high-density PCB layout design while ensuring signal integrity and ...
Quick apply
PCB Design Engineer
Irvine, CA ยท On-site
PCB Design Engineer Location : Irvine, California, 100% onsite Position type: Contract Visa: US ... Perform high-speed and high-density PCB layout design while ensuring signal integrity and ...
ASIC Physical Design Engineer
$159K - $164K/yr
... high-caliber ASIC Physical Design Engineer to spearhead the structural realization of next ... Formalize and validate pre-layout timing constraints to ensure architectural feasibility and ...
ASIC Physical Design Engineer
$159K - $164K/yr
... high-caliber ASIC Physical Design Engineer to spearhead the structural realization of next ... Formalize and validate pre-layout timing constraints to ensure architectural feasibility and ...
Sr. Analog Design Engineer
$156K - $160K/yr
... as asic_pixel array, column-bias generation, rampbuffer, column-amplifier, comparator, ramp ... Collaborate with layout engineer on whole chip layout integration, verification, and improvement.
Sr. Analog Design Engineer
$156K - $160K/yr
... as asic_pixel array, column-bias generation, rampbuffer, column-amplifier, comparator, ramp ... Collaborate with layout engineer on whole chip layout integration, verification, and improvement.
Sr. Analog Design Engineer
$156K - $160K/yr
... as asic_pixel array, column-bias generation, rampbuffer, column-amplifier, comparator, ramp ... Collaborate with layout engineer on whole chip layout integration, verification, and improvement.
Sr. Analog Design Engineer
$156K - $160K/yr
... as asic_pixel array, column-bias generation, rampbuffer, column-amplifier, comparator, ramp ... Collaborate with layout engineer on whole chip layout integration, verification, and improvement.
Sr. Analog Design Engineer
Santa Clara, CA ยท On-site
$156K - $160K/yr
... as asic_pixel array, column-bias generation, rampbuffer, column-amplifier, comparator, ramp ... Collaborate with layout engineer on whole chip layout integration, verification, and improvement.
Sr. Analog Design Engineer
Santa Clara, CA ยท On-site
$156K - $160K/yr
... as asic_pixel array, column-bias generation, rampbuffer, column-amplifier, comparator, ramp ... Collaborate with layout engineer on whole chip layout integration, verification, and improvement.
... as asic_pixel array, column-bias generation, rampbuffer, column-amplifier, comparator, ramp ... Collaborate with layout engineer on whole chip layout integration, verification, and improvement.
Quick apply
... as asic_pixel array, column-bias generation, rampbuffer, column-amplifier, comparator, ramp ... Collaborate with layout engineer on whole chip layout integration, verification, and improvement.
ASIC Design Engineer - Staff
Irvine, CA ยท On-site
$150K - $250K/yr
Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to the development of optical transceivers for next-generation optical modems. The ideal candidate will ...
ASIC Design Engineer - Staff
Irvine, CA ยท On-site
$150K - $250K/yr
Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to the development of optical transceivers for next-generation optical modems. The ideal candidate will ...
ASIC Design Engineer - Staff
$150K - $250K/yr
Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to the development of optical transceivers for next-generation optical modems. The ideal candidate will ...
ASIC Design Engineer - Staff
$150K - $250K/yr
Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to the development of optical transceivers for next-generation optical modems. The ideal candidate will ...
ASIC RTL/SoC Design Engineer
$110K - $300K/yr
Experience with pre-layout simulation and post-layout simulation * Understanding of the design flow ... FPGA/ASIC design of image processing systems * Working knowledge of SoC architecture such as CPU ...
ASIC RTL/SoC Design Engineer
$110K - $300K/yr
Experience with pre-layout simulation and post-layout simulation * Understanding of the design flow ... FPGA/ASIC design of image processing systems * Working knowledge of SoC architecture such as CPU ...
ASIC Design Engineer (Onsite)
$165K - $241K/yr
YOUR IMPACT Define, design and take end to end Front-End ownership of ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the ...
ASIC Design Engineer (Onsite)
$165K - $241K/yr
YOUR IMPACT Define, design and take end to end Front-End ownership of ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the ...
Exciting Opportunity for Analog Layout Design engineer_ bay area, CA
San Francisco, CA ยท On-site
$238K/yr
Analog Layout Design engineer Location : bay area, CA - onsite Responsibilities: * Minimum 15+ years of related experience with an associate degree. * Own and Execute the layout design of analog ...
Quick apply
Exciting Opportunity for Analog Layout Design engineer_ bay area, CA
San Francisco, CA ยท On-site
$238K/yr
Analog Layout Design engineer Location : bay area, CA - onsite Responsibilities: * Minimum 15+ years of related experience with an associate degree. * Own and Execute the layout design of analog ...
ASIC RTL/SoC Design Engineer
San Jose, CA ยท On-site
$110K - $300K/yr
Experience with pre-layout simulation and post-layout simulation * Understanding of the design flow ... FPGA/ASIC design of image processing systems * Working knowledge of SoC architecture such as CPU ...
ASIC RTL/SoC Design Engineer
San Jose, CA ยท On-site
$110K - $300K/yr
Experience with pre-layout simulation and post-layout simulation * Understanding of the design flow ... FPGA/ASIC design of image processing systems * Working knowledge of SoC architecture such as CPU ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to ...
Asic Layout Design Engineer information
See California salary details
$44.4K - $57K
4% of jobs
$57K - $69.6K
2% of jobs
$69.6K - $82.2K
12% of jobs
$92.5K is the 25th percentile. Wages below this are outliers.
$82.2K - $94.8K
9% of jobs
$94.8K - $107.4K
11% of jobs
The median wage is $119.1K / yr.
$107.4K - $120K
14% of jobs
$120K - $132.6K
22% of jobs
$135K is the 75th percentile. Wages above this are outliers.
$132.6K - $145.3K
9% of jobs
$145.3K - $157.9K
9% of jobs
$157.9K - $170.5K
3% of jobs
$170.5K - $183.1K
6% of jobs
$44.4K
$119.3K
$183.1K
How much do asic layout design engineer jobs pay per year?
What are ASIC Layout Design Engineers?
What are the key skills and qualifications needed to thrive as an ASIC Layout Design Engineer, and why are they important?
What are some common challenges faced by ASIC Layout Design Engineers in managing complex projects?
What is the difference between Asic Layout Design Engineer vs Digital IC Design Engineer?
| Aspect | Asic Layout Design Engineer | Digital IC Design Engineer |
|---|---|---|
| Primary Focus | Physical layout and placement of ASIC components | Logical design and architecture of digital circuits |
| Skills Required | EDA tools, layout optimization, fabrication process knowledge | HDL coding, simulation, digital logic design |
| Work Environment | ASIC design teams, fabrication facilities | Design houses, semiconductor companies |
| Certifications | Typically none specific, but familiarity with industry standards | HDL certifications, digital design courses |
While both roles are integral to ASIC development, the Asic Layout Design Engineer focuses on the physical implementation of circuits, ensuring manufacturability and performance. In contrast, the Digital IC Design Engineer concentrates on the logical design and verification of digital circuits. Both roles require knowledge of digital design principles, but their daily tasks and skill sets differ significantly.
Full-time
Posted 25 days ago
Job description
We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and multifaceted group of diverse individuals responsible for handling meaningful high-speed mixed-signal circuit designs. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities that are hard to take on, that only we can pursue, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. We would love to hear from you!
What you'll be doing:
- Performing physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog to Digital converters, ESD structures designs in innovative sub-micron CMOS technologies using Cadence tools.
- You'll work multi-functional with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
- Take part in floor planning, custom layout and verifying against design rules and schematics.
What we need to see:
- Have a BSEE or equivalent experience and minimum of 8+ years industry experience.
- Deep understanding of analog circuit layout concepts in submicron CMOS technologies.
- You are an authority with Cadence custom circuit design tools
- Experience running and debugging with verification tools such as Dracula, Hercules, Calibre, and Primeyield.
- You are able to work optimally in a team, good interpersonal skills, passion and positive energy.
- Proficient in scripting languages like perl, python, skill etc.
- Should have knowledge of DRC and LVS checking flows, ability to customize decks.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 132,000 USD - 207,000 USD.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until May 9, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1993