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Asic Layout Design Engineer Jobs in California (NOW HIRING)

Qualcomm

ASIC Design Engineer

Santa Clara, CA · On-site

$126.70 - $190.10/hr

Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience * Master's degree in Science, Engineering ...

Fusion408

Principal ASIC Design Engineer

Carlsbad, CA · On-site

Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...

Fusion408

Principal ASIC Design Engineer

Carlsbad, CA · On-site

Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...

TetraMem INC

ASIC RTL/SoC Design Engineer

Fremont, CA · On-site

Experience with pre-layout simulation and post-layout simulation * Understanding of the design flow ... FPGA/ASIC design of image processing systems * Working knowledge of SoC architecture such as CPU ...

TetraMem INC

ASIC RTL/SoC Design Engineer

Fremont, CA · On-site

Experience with pre-layout simulation and post-layout simulation * Understanding of the design flow ... FPGA/ASIC design of image processing systems * Working knowledge of SoC architecture such as CPU ...

Nvidia

Senior ASIC Design Engineer

Santa Clara, CA · Hybrid

We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of ...

OMNIVISION

Sr. Analog Design Engineer

Santa Clara, CA

$156K - $160K/yr

... as asic_pixel array, column-bias generation, rampbuffer, column-amplifier, comparator, ramp ... Collaborate with layout engineer on whole chip layout integration, verification, and improvement.

OMNIVISION

Sr. Analog Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

... as asic_pixel array, column-bias generation, rampbuffer, column-amplifier, comparator, ramp ... Collaborate with layout engineer on whole chip layout integration, verification, and improvement.

Qualcomm

ASIC Design Engineer

Santa Clara, CA · On-site

$126K - $190K/yr

OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related ...

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Asic Layout Design Engineer information

What is an ASIC layout design engineer?

ASIC Layout Design Engineers are specialized professionals who create the physical design of Application-Specific Integrated Circuits (ASICs). They translate circuit schematics into geometric representations that can be fabricated onto silicon chips, ensuring performance, power, and area specifications are met. Their work involves using electronic design automation (EDA) tools to place and route circuit elements while adhering to manufacturing constraints and design rules. They collaborate closely with circuit designers and verification engineers throughout the chip design process.

What are the key skills and qualifications needed to thrive as an ASIC layout design engineer, and why are they important?

To thrive as an ASIC Layout Design Engineer, you need expertise in semiconductor physics, VLSI design, and layout methodologies, typically supported by a degree in electrical engineering or a related field. Proficiency with EDA tools such as Cadence Virtuoso, Mentor Graphics, and knowledge of process design kits (PDKs) are routinely required. Attention to detail, strong problem-solving abilities, and effective collaboration skills help engineers excel in this role. These skills are crucial for ensuring accurate, efficient, and manufacturable chip designs that meet performance and reliability standards.

What are some common challenges faced by an ASIC layout design engineer in managing complex projects?

ASIC Layout Design Engineers often face challenges such as meeting tight design schedules, ensuring design rule compliance, and minimizing layout-induced circuit issues like parasitics and crosstalk. Balancing these technical demands with iterative feedback from verification and design teams requires effective communication and strong problem-solving skills. Additionally, staying updated with evolving EDA tools and process technologies is essential for delivering high-quality layouts within project constraints.

What is the difference between Asic Layout Design Engineer vs Digital IC Design Engineer?

AspectAsic Layout Design EngineerDigital IC Design Engineer
Primary FocusPhysical layout and placement of ASIC componentsLogical design and architecture of digital circuits
Skills RequiredEDA tools, layout optimization, fabrication process knowledgeHDL coding, simulation, digital logic design
Work EnvironmentASIC design teams, fabrication facilitiesDesign houses, semiconductor companies
CertificationsTypically none specific, but familiarity with industry standardsHDL certifications, digital design courses

While both roles are integral to ASIC development, the Asic Layout Design Engineer focuses on the physical implementation of circuits, ensuring manufacturability and performance. In contrast, the Digital IC Design Engineer concentrates on the logical design and verification of digital circuits. Both roles require knowledge of digital design principles, but their daily tasks and skill sets differ significantly.

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What job categories do people searching Asic Layout Design Engineer jobs in California look for? The top searched job categories for Asic Layout Design Engineer jobs in California are:
Asic Layout Design Engineer jobs near you
Infographic showing various Asic Layout Design Engineer job openings in California as of August 2026, with employment types broken down into 1% Internship, 85% Full Time, 8% Part Time, 2% Temporary, and 4% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution.

ASIC Design Engineer

Qualcomm

Santa Clara, CA • On-site

$126.70 - $190.10/hr

Other

Re-posted yesterday

Qualcomm rating

8.8

Company rating: 8.8 out of 10

Based on 11 frontline employees who took The Breakroom Quiz

49th of 244 rated software companies

Job description

Company

Qualcomm Atheros, Inc.

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

Qualcomm-Atheros, a.k.a. QCA is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast‑paced Integrated Wireless Technology team you will be working with WiFi (802.11x) technology, SOC infrastructure, chip level verification and employ best‑in‑class Design and verification methodology.

Responsibilities

The candidate will be responsible for micro‑architecture, RTL design, and development of new functional blocks, as well as subsystem and full‑chip integration. This role is hands‑on and requires ownership of the design through the complete ASIC lifecycle, from concept through tape‑out. The candidate will collaborate closely with other subsystem teams to ensure smooth integration of releases, while interfacing with verification, DFT, FPGA emulation, and implementation teams.

Required Skills
  • 5+ years of industry experience in ASIC design, micro‑architecture, and design integration
  • Strong background in SoC micro‑architecture, including specification, definition, and implementation of functional blocks
  • Hands‑on experience with multi‑domain clocking implementation in SOCs including understanding of clocking architectures, clock/power domain partitioning
  • Experience in Design linting and CDC analysis, including triage and closure of violations
  • Solid understanding of AMBA bus protocols, including AHB and APB
  • Proficiency in Python/Perl is required
  • Exposure to AI/ML based design methodologies is a strong plus
Minimum Qualifications
  • Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience
  • Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience
  • PhD in Science, Engineering, or related field
Preferred Skills
  • Experience with ARM CoreSight architecture and debug interfaces
  • Experience with AXI Bus protocol
  • Experience with PCIe and/or USB peripheral subsystems
  • Low Power design and implementation
  • Chip interconnect (NOC) implementation
Pay range and Other Compensation & Benefits

$126,700.00 - $190,100.00. The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants. In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play.

EEO Statement

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

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About Qualcomm

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Qualcomm is enabling a world where everyone and everything can be intelligently connected. You interact with products and technologies made possible by Qualcomm every day, including 5G-enabled smartphones that double as pro-level cameras and gaming devices, smarter vehicles and cities, and the technology behind the smart, connected factories that manufactured your latest purchase. Our powerful connectivity solutions keep you connected—even in remote areas. Qualcomm 5G and AI innovations are the power behind the connected intelligent edge. You’ll find our technologies behind and inside the innovations that deliver significant value across multiple industries and to billions of people every day.

Industry

Technology, communication and media

Company size

10,000+ Employees

Headquarters location

San Diego, CA, US

Year founded

1985

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