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Asic Layout Design Engineer Jobs in California (NOW HIRING)

Nvidia

Senior Mask Design Engineer

Santa Clara, CA · Hybrid

$122K - $164K/yr

You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. * Job duties will include floor planning, custom layout and verifying against design rules and ...

Nvidia Corporation

Senior Mask Design Engineer

Santa Clara, CA · On-site

$122K - $164K/yr

You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. * Job duties will include floor planning, custom layout and verifying against design rules and ...

Fusion408

Principal ASIC Design Engineer

Carlsbad, CA · On-site

Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...

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$44.4K

$119.3K

$183.1K

How much do asic layout design engineer jobs pay per year?

As of Jun 11, 2026, the average yearly pay for asic layout design engineer in California is $119,266.00, according to ZipRecruiter salary data. Most workers in this role earn between $88,800.00 and $142,100.00 per year, depending on experience, location, and employer.

What are ASIC Layout Design Engineers?

ASIC Layout Design Engineers are specialized professionals who create the physical design of Application-Specific Integrated Circuits (ASICs). They translate circuit schematics into geometric representations that can be fabricated onto silicon chips, ensuring performance, power, and area specifications are met. Their work involves using electronic design automation (EDA) tools to place and route circuit elements while adhering to manufacturing constraints and design rules. They collaborate closely with circuit designers and verification engineers throughout the chip design process.

What are the key skills and qualifications needed to thrive as an ASIC Layout Design Engineer, and why are they important?

To thrive as an ASIC Layout Design Engineer, you need expertise in semiconductor physics, VLSI design, and layout methodologies, typically supported by a degree in electrical engineering or a related field. Proficiency with EDA tools such as Cadence Virtuoso, Mentor Graphics, and knowledge of process design kits (PDKs) are routinely required. Attention to detail, strong problem-solving abilities, and effective collaboration skills help engineers excel in this role. These skills are crucial for ensuring accurate, efficient, and manufacturable chip designs that meet performance and reliability standards.

What are some common challenges faced by ASIC Layout Design Engineers in managing complex projects?

ASIC Layout Design Engineers often face challenges such as meeting tight design schedules, ensuring design rule compliance, and minimizing layout-induced circuit issues like parasitics and crosstalk. Balancing these technical demands with iterative feedback from verification and design teams requires effective communication and strong problem-solving skills. Additionally, staying updated with evolving EDA tools and process technologies is essential for delivering high-quality layouts within project constraints.

What is the difference between Asic Layout Design Engineer vs Digital IC Design Engineer?

AspectAsic Layout Design EngineerDigital IC Design Engineer
Primary FocusPhysical layout and placement of ASIC componentsLogical design and architecture of digital circuits
Skills RequiredEDA tools, layout optimization, fabrication process knowledgeHDL coding, simulation, digital logic design
Work EnvironmentASIC design teams, fabrication facilitiesDesign houses, semiconductor companies
CertificationsTypically none specific, but familiarity with industry standardsHDL certifications, digital design courses

While both roles are integral to ASIC development, the Asic Layout Design Engineer focuses on the physical implementation of circuits, ensuring manufacturability and performance. In contrast, the Digital IC Design Engineer concentrates on the logical design and verification of digital circuits. Both roles require knowledge of digital design principles, but their daily tasks and skill sets differ significantly.

What are popular job titles related to Asic Layout Design Engineer jobs in California? For Asic Layout Design Engineer jobs in California, the most frequently searched job titles are:
What job categories do people searching Asic Layout Design Engineer jobs in California look for? The top searched job categories for Asic Layout Design Engineer jobs in California are:
Asic Layout Design Engineer jobs near you
Senior Photonic Layout Design Engineer

Senior Photonic Layout Design Engineer

Nvidia

Santa Clara, CA

Full-time

Posted 23 days ago

Job description

Are you seeking an outstanding opportunity? We are looking for a Senior Photonic Layout Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling high-speed mixed-signal & Silicon Photonic Designs! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. Join our diverse team today!

What You'll Be Doing:

  • As a Senior Photonics Layout Engineer, you will take ownership of the physical design and verification of cutting-edge photonic integrated circuits (PICs), guiding designs from initial proof-of-concept phases to high-volume manufacturing readiness. You will work within a highly collaborative, multidisciplinary team of photonics, CMOS, packaging, and systems engineers to drive next-generation Silicon Photonics (SiPh) and SERDES products.

  • Layout Execution & Tape-out Ownership: Lead complex, full-loop manual and automated layout designs for waveguides, modulators, photodetectors, and mixed-signal functions (high-speed/general I/Os, ESD structures). Drive the full tape-out process, including floor planning, waveguide routing, and mask data preparation.

  • Verification & Mitigation: Execute rigorous post-layout verification (DRC, LVS, fill, density) across multiple stepping versions. Trace defect sources, mitigate layout-dependent issues, and ensure DRC/LVS cleanliness prior to tape-out.

  • Test Vehicle & Component Development: Own the layout of complex test structures, active/passive full loops, and certification vehicles with large Design of Experiments (DOEs) to optimize for process windows.

  • Automation & AI-Assisted Workflows: Develop and implement AI-assisted design methods, layout automation scripts, and custom Pcells to improve productivity, reduce development cycle times, and customize DRC/LVS checking flows.

What We Need to See:

  • To succeed in this role, candidates must possess a deep technical understanding of advanced node semiconductor fabrication, sophisticated automation capabilities, and a proven track record of first-time success on high-density chip designs.

  • BS, MS, or Ph.D. in Electrical Engineering, Physics, or a closely related field (or equivalent experience). At least 6+ years of hands-on, full-chip layout design experience in semiconductor, analog, or silicon photonics industries.

  • Deep understanding of analog circuit layout, Silicon Photonic constraints, and device physics within advanced sub-micron CMOS and SiPh technologies.

  • Proven expertise with Cadence Virtuoso (Custom Layout, SDL) and industry-standard verification suites (Calibre, Hercules, ICV, Dracula, or Primeyield).

  • Strong proficiency in programming and scripting languages (Python, SKILL, Perl, TCL, or C++) for layout automation, file I/O, data processing, and tape-out flows.

  • Ability to optimize workflows using best-known methods (BKMs), and proactively collaborate with integration, and design rule teams to achieve high-yield manufacturing goals.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 132,000 USD - 207,000 USD for Level 4, and 148,000 USD - 235,750 USD for Level 5.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until May 22, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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About Nvidia

Sourced by ZipRecruiter

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1993

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