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Dft Engineer Jobs (NOW HIRING)

CA-One Tech Cloud Inc.

DFT Engineer

San Jose, CA · On-site

Senior DFT Enginner San Jose, CA Position Summary We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory ...

Broadcom Corporation

DFT Engineer

Austin, TX · On-site

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

Work closely with the ATE engineer on yield improvement and analysis. * Develop ATE patterns, manage the hand-off process, and perform silicon debugging. * Participate in block and chip-level DFT ...

New

NXP Semiconductors

Senior DfT Engineer

Chandler, AZ · On-site

$120 - $160/hr

R-10064841As a DfT engineer, you will join a highly experienced team. Your key responsibilities will be:1) Closely collaborate with Product Definer, Analog Design Lead, Digital Design Lead, Test Lead ...

Purple Hires Inc

ASIC DFT Engineer

Irvine, CA · On-site

Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation. * Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and ...

Vkore Solutions

Lead ASIC DFT Engineer

San Jose, CA · On-site

Role: Lead ASIC DFT Engineer Location: Remote Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to ...

NXP Semiconductors

Senior DfT Engineer

Chandler, AZ · On-site

As a DfT engineer, you will join a highly experienced team. Your key responsibilities will be: 1) Closely collaborate with Product Definer, Analog Design Lead, Digital Design Lead, Test Lead, Product ...

Broadcom, Inc.

DFT Engineer

Austin, TX · On-site

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

Work closely with the ATE engineer on yield improvement and analysis. * Develop ATE patterns, manage the hand-off process, and perform silicon debugging. * Participate in block and chip-level DFT ...

GlobalFoundries

DFT Engineer

Austin, TX · On-site

$106K - $184K/yr

The DFT Engineer delivers hands-on expertise in designing and deploying advanced Design-for-Test solutions for semiconductor chip development. This role drives robust DFT architectures-including ATPG ...

Purple Hires Inc

Lead ASIC DFT Engineer

San Jose, CA · Remote

Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Below is the detailed for your reference - Experience 10+ years of hands-on experience in ASIC Design-for-Test ...

K2 Space

Senior DFT Engineer

OR · On-site +1

$170K - $250K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...

Apple

SoC DFT Engineer

Austin, TX · On-site

Description As a DFT engineer you will be involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. - Developing and ...

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All JobsDft Engineer Jobs

DFT Engineer information

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$73K

$129.5K

$249K

How much do dft engineer jobs pay per year?

As of Aug 16, 2026, the average yearly pay for dft engineer in the United States is $129,511.00, according to ZipRecruiter salary data. Most workers in this role earn between $103,000.00 and $134,500.00 per year, depending on experience, location, and employer.

What is a DFT engineer?

DFT Engineers, or Design for Test Engineers, are professionals who specialize in designing and implementing test structures and methodologies within integrated circuits (ICs) to ensure their testability and reliability during manufacturing. Their work enables efficient detection and diagnosis of faults in chips, helping to improve yield and reduce production costs. DFT Engineers collaborate closely with design, verification, and manufacturing teams to integrate features such as scan chains, built-in self-test (BIST), and boundary scan into chip designs. Their expertise is crucial for modern semiconductor development, especially as chips become increasingly complex.

What are the key skills and qualifications needed to thrive as a DFT engineer?

To thrive as a DFT (Design for Test) Engineer, you need a solid background in electrical engineering, digital design, and ASIC/FPGA development, often supported by a relevant degree. Familiarity with test methodologies, scan insertion tools (such as Synopsys DFT Compiler or Mentor Tessent), and scripting languages like Perl or Python is typically required. Strong problem-solving skills, attention to detail, and effective communication help DFT Engineers collaborate with design and verification teams to resolve complex testability challenges. These competencies are essential to ensure high-quality, testable silicon designs that minimize defects and streamline manufacturing processes.

What are some common challenges faced by DFT engineers during the silicon validation phase, and how can these be addressed?

DFT Engineers often encounter challenges during the silicon validation phase, such as discrepancies between simulation results and actual silicon behavior, limited access to internal nodes, and diagnosing scan chain failures. These issues can be addressed by thorough pre-silicon verification, incorporating robust test points, and leveraging advanced diagnostic tools and methodologies. Effective collaboration with design and validation teams is also crucial to quickly resolve issues and implement necessary design changes, ensuring high test coverage and product reliability.

What is the difference between Dft Engineer vs Test Engineer?

AspectDft EngineerTest Engineer
Required CredentialsBachelor's in Electronics, Electrical, or related fields; certifications in DFT techniquesBachelor's in Electronics, Electrical, Computer Science; certifications in testing methodologies
Work EnvironmentDesign and implementation of DFT strategies during IC developmentTesting, validation, and debugging of electronic products and systems
Employer & Industry UsageSemiconductor companies, IC design firmsConsumer electronics, automotive, telecommunications industries

While both Dft Engineers and Test Engineers work in electronics and semiconductor industries, Dft Engineers focus on designing testability features during chip development, whereas Test Engineers execute testing and validation of finished products. Their roles complement each other, but their daily tasks and expertise areas differ significantly.

How much do DFT engineers make?

Design for Test (DFT) engineers typically earn between $80,000 and $130,000 annually, depending on experience, location, and industry. Senior DFT engineers with specialized skills in automation and verification can earn higher salaries, especially in high-demand tech regions.

Is DFT engineering a good career?

DFT (Design for Test) engineering is a specialized field within semiconductor and integrated circuit design, focusing on ensuring chip testability and manufacturability. It offers steady demand due to the need for quality control in electronics manufacturing and typically requires knowledge of digital design, testing methodologies, and tools like EDA software. Career growth depends on industry trends, technical skills, and certifications, making it a viable option for those interested in hardware design and testing.

What does a Dft engineer do?

A DFT (Design for Test) engineer designs and implements testing strategies to ensure integrated circuits and electronic systems are defect-free and function correctly. They develop test plans, create test hardware and software, and work closely with design teams to improve testability and reduce manufacturing defects. Proficiency in scripting, testing tools, and industry standards is essential for this role.
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DFT Engineer jobs near you
Infographic showing various Dft Engineer job openings in the United States as of August 2026, with employment types broken down into 92% Full Time, 2% Part Time, and 6% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $129,511 per year, or $62.3 per hour.

DFT Engineer

CA-One Tech Cloud Inc.

San Jose, CA • On-site

Other

Posted 6 days ago

Job description

Senior DFT Enginner
San Jose, CA
Position Summary
We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision.
Responsibilities
Perform MBIST insertion for complex SoC designs using Synopsys SMS.
Integrate and verify MBIST at the top level.
Develop, execute, and debug MBIST simulations using Synopsys VCS, including:
RTL
No-delay gate level simulations
With-delay (timing-aware) simulations
Generate and validate MBIST test patterns using Vecgen.
Debug RTL, simulation, and MBIST integration issues.
Support silicon bring-up, characterization, and post-silicon debug related to MBIST, memory failures, and DFT infrastructure.
Work closely with DFT, RTL, Physical Design, and Product Engineering teams to resolve implementation issues.
Drive issue resolution independently and document implementation flows and debug findings.
Required Qualifications
8+ years of hands-on DFT experience, with significant focus on MBIST.
Strong experience with Synopsys MBIST (SMS), preferably SMS6 and/or SMS5.
Proficiency with Synopsys VCS for MBIST verification and simulation.
Deep understanding of the complete MBIST flow:
MBIST insertion
Top-level integration
Verification
Pattern generation (Vecgen)
Diagnostics
Simulation and debug
Strong understanding of MBIST test algorithms (e.g., March algorithms) and memory repair schemes (BIRA/BISR, redundancy analysis, spare row/column allocation).
Experience running and debugging:
No-delay simulations
With-delay simulations
Experience supporting silicon bring-up, post-silicon debug, and root-cause analysis of MBIST and memory-related failures.
Strong debugging and root-cause analysis skills across RTL, MBIST, and simulation environments.
Ability to work independently with minimal supervision.
Experience with large, complex SoC designs containing multiple memory instances.
Familiarity with Verilog/SystemVerilog and standard DFT methodologies.
Preferred Qualifications
Experience with advanced SoC DFT integration.
Familiarity with ATPG and scan insertion flows.
Experience with scripting (Tcl, Perl, or Python) to automate MBIST flows and debug.
Experience working in fast-paced semiconductor product development.
Key Skills
Synopsys MBIST (SMS5/SMS6)
Synopsys VCS
MBIST insertion
Top-level MBIST verification
VecGen pattern generation
MBIST diagnostics
MBIST repair schemes and memory test algorithms
No-delay, with-delay simulation and debug
Silicon bring-up and post-silicon debug
SoC DFT integration
Tcl / Perl / Python scripting
Strong communication skills
Self-motivated and capable of working independently
Ideal Candidate
The ideal contractor is a senior, hands-on MBIST engineer who can quickly become productive with minimal ramp-up. They should have deep experience with Synopsys SMS and VCS, excellent debugging skills, strong communication abilities, and a proven track record of independently delivering MBIST implementation, verification, and debug for complex SoC designs.
 
 
 
Thanks & Regards,
 
Pankaj Singh - Team Lead
CA-One Tech Cloud Inc. | CA-One.com | E- Verified Company
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