About Cadence Design Systems
Sourced by ZipRecruiter
Industry
Software development
Company size
5,001 - 10,000 Employees
Headquarters location
San Jose, CA, US
Year founded
1988
$134.80K - $164.50K/yr
Full-time
Posted 16 days ago
Job description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Design Verification Lead Engineer
Role Overview:
The Lead DV Engineer focuses on the execution and technical management of verification projects. You will lead a focused team to ensure comprehensive test coverage and closure for specific CPU cores or processor blocks.
Key Responsibilities:
Required Qualifications:
Design Verification Lead Engineer
Role Overview:
The Lead DV Engineer focuses on the execution and technical management of verification projects. You will lead a focused team to ensure comprehensive test coverage and closure for specific CPU cores or processor blocks.
Key Responsibilities:
- Technical Execution: Developing and executing detailed verification plans (vPlans) using Cadence vManager.
- Environment Development: Develop UVM scoreboards, monitors, and complex functional coverage models for multi-protocol or processor-specific interfaces.
- Debug & Triage: Lead the debug of complex RTL failures and coordinate with design engineers to resolve microarchitectural bugs.
- Regression Management: Manage automated regression environments (e.g., Jenkins) and ensure targets for code and functional coverage are met.
- Project Tracking: Responsible for technical alignment, project planning, and progress tracking for the verification lifecycle.
Required Qualifications:
- B.S/M.S in EEE with 5-8+ years of hands-on experience in VLSI design verification.
- Strong command of SystemVerilog Assertions (SVA), constraint randomization, and UVM.
- Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe.
- Expertise in scripting (Perl, Python, or Tcl) for verification flow automation.
cadence.com
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Frequently asked questions
Q: What skills or qualities help someone succeed as a Design Verification Engineer?
A: To succeed as a Design Verification Engineer, key technical skills include proficiency in programming languages such as C, C++, or Python, as well as experience with verification tools like UVM, SystemVerilog, or Verilog. Additionally, strong analytical and problem-solving skills, along with knowledge of digital design principles and methodologies, are essential for identifying and resolving design issues. Soft skills like effective communication, collaboration, and attention to detail also contribute to success in this role, enabling Design Verification Engineers to work closely with cross-functional teams and ensure high-quality product releases.
Q: What is the career path for a Design Verification Engineer?
A: A Design Verification Engineer's typical career progression involves starting as a Verification Engineer, where they develop and execute test plans to ensure product functionality, then advancing to a Senior Verification Engineer or Verification Lead, overseeing verification teams and processes. Along the way, they can develop skills in programming languages, such as C, C++, or Python, as well as expertise in verification tools and methodologies, like UVM or SystemVerilog. With experience, they can transition into senior roles, such as Verification Manager or Technical Lead, or explore adjacent fields like Engineering Management or Technical Consulting.
