VLSI Design Verification Manager - Slingshot ASIC Team This role has been designed as ''Onsite ... In this role, you will lead a team of design verification engineers responsible for ensuring ...
VLSI Design Verification Manager - Slingshot ASIC Team This role has been designed as ''Onsite ... In this role, you will lead a team of design verification engineers responsible for ensuring ...
VLSI Design Verification Manager - Slingshot ASIC Team This role has been designed as ''Onsite ... In this role, you will lead a team of design verification engineers responsible for ensuring ...
VLSI Design Verification Manager - Slingshot ASIC Team This role has been designed as ''Onsite ... In this role, you will lead a team of design verification engineers responsible for ensuring ...
GPU Formal Design Verification Engineer
Austin, TX · On-site
$134.80K - $164.50K/yr
The Graphics Verification Engineer will be responsible for the pre-silicon RTL verification ... Knowledge of CPU or GPU design architectures, VLSI circuits, and digital logic design.Experience ...
GPU Formal Design Verification Engineer
Austin, TX · On-site
$134.80K - $164.50K/yr
The Graphics Verification Engineer will be responsible for the pre-silicon RTL verification ... Knowledge of CPU or GPU design architectures, VLSI circuits, and digital logic design.Experience ...
GPU Formal Design Verification Engineer
$134.80K - $164.50K/yr
The Graphics Verification Engineer will be responsible for the pre-silicon RTL verification ... Preferred Qualifications Knowledge of CPU or GPU design architectures, VLSI circuits, and digital ...
GPU Formal Design Verification Engineer
$134.80K - $164.50K/yr
The Graphics Verification Engineer will be responsible for the pre-silicon RTL verification ... Preferred Qualifications Knowledge of CPU or GPU design architectures, VLSI circuits, and digital ...
GPU Formal Design Verification Engineer
Austin, TX · On-site
$134.80K - $164.50K/yr
Experience with CPU or GPU design architectures, VLSI circuits, and digital logic design.Experience with formal verification tools, such as JasperGold, IFV, etc.Experience in programming/scripting ...
GPU Formal Design Verification Engineer
Austin, TX · On-site
$134.80K - $164.50K/yr
Experience with CPU or GPU design architectures, VLSI circuits, and digital logic design.Experience with formal verification tools, such as JasperGold, IFV, etc.Experience in programming/scripting ...
GPU Formal Design Verification Engineer
$134.80K - $164.50K/yr
Experience with CPU or GPU design architectures, VLSI circuits, and digital logic design. Experience with formal verification tools, such as JasperGold, IFV, etc. Experience in programming/scripting ...
GPU Formal Design Verification Engineer
$134.80K - $164.50K/yr
Experience with CPU or GPU design architectures, VLSI circuits, and digital logic design. Experience with formal verification tools, such as JasperGold, IFV, etc. Experience in programming/scripting ...
Formal Verification Engineer
$181.10K - $318.40K/yr
Preferred Qualifications Hands on experience with VLSI and digital logic design and verification ... engineering or related field. Pay & Benefits At Apple, base pay is one part of our total ...
Formal Verification Engineer
$181.10K - $318.40K/yr
Preferred Qualifications Hands on experience with VLSI and digital logic design and verification ... engineering or related field. Pay & Benefits At Apple, base pay is one part of our total ...
Formal Verification Engineer
$147.40K - $272.10K/yr
Preferred Qualifications Hands on experience with VLSI and digital logic design and verification ... engineering or related field. Pay & Benefits At Apple, base pay is one part of our total ...
Formal Verification Engineer
$147.40K - $272.10K/yr
Preferred Qualifications Hands on experience with VLSI and digital logic design and verification ... engineering or related field. Pay & Benefits At Apple, base pay is one part of our total ...
Formal Verification Engineer
$147.40K - $272.10K/yr
Preferred Qualifications Hands on experience with VLSI and digital logic design and verification ... engineering or related field. Pay & Benefits At Apple, base pay is one part of our total ...
Formal Verification Engineer
$147.40K - $272.10K/yr
Preferred Qualifications Hands on experience with VLSI and digital logic design and verification ... engineering or related field. Pay & Benefits At Apple, base pay is one part of our total ...
Formal Verification Engineer
$181.10K - $318.40K/yr
Preferred Qualifications Hands on experience with VLSI and digital logic design and verification ... engineering or related field. Pay & Benefits At Apple, base pay is one part of our total ...
Formal Verification Engineer
$181.10K - $318.40K/yr
Preferred Qualifications Hands on experience with VLSI and digital logic design and verification ... engineering or related field. Pay & Benefits At Apple, base pay is one part of our total ...
Principal Verification Engineer (San Jose)
San Jose, CA · Hybrid
$170K - $196K/yr
Define verification plans in coordination with Architects, Logic, and Mixed-Signal Designers ... VLSI Design Engineer (Physical Design, New College Grad, Masters) Electrical Engineer/Senior ...
Principal Verification Engineer (San Jose)
San Jose, CA · Hybrid
$170K - $196K/yr
Define verification plans in coordination with Architects, Logic, and Mixed-Signal Designers ... VLSI Design Engineer (Physical Design, New College Grad, Masters) Electrical Engineer/Senior ...
Formal Verification Engineer
$181.10K - $318.40K/yr
Preferred Qualifications Hands on experience with VLSI and digital logic design and verification ... engineering or related field. Pay & Benefits At Apple, base pay is one part of our total ...
Formal Verification Engineer
$181.10K - $318.40K/yr
Preferred Qualifications Hands on experience with VLSI and digital logic design and verification ... engineering or related field. Pay & Benefits At Apple, base pay is one part of our total ...
Formal Verification Engineer
$147.40K - $272.10K/yr
Preferred Qualifications Hands on experience with VLSI and digital logic design and verification ... engineering or related field. Pay & Benefits At Apple, base pay is one part of our total ...
Formal Verification Engineer
$147.40K - $272.10K/yr
Preferred Qualifications Hands on experience with VLSI and digital logic design and verification ... engineering or related field. Pay & Benefits At Apple, base pay is one part of our total ...
Silicon Design Verification Engineer
Austin, TX · Hybrid
$134.80K - $164.50K/yr
The Verification Engineering team furthers and encourages continuous technical innovation to ... VLSI designs is a plus. * Experience with gate level simulation, power verification, reset ...
Silicon Design Verification Engineer
Austin, TX · Hybrid
$134.80K - $164.50K/yr
The Verification Engineering team furthers and encourages continuous technical innovation to ... VLSI designs is a plus. * Experience with gate level simulation, power verification, reset ...
Silicon Design Verification Engineer
San Jose, CA · On-site
$124.04K/yr
The Verification Engineering team furthers and encourages continuous technical innovation to ... VLSI designs is a plus. * Experience with gate level simulation, power verification, reset ...
Silicon Design Verification Engineer
San Jose, CA · On-site
$124.04K/yr
The Verification Engineering team furthers and encourages continuous technical innovation to ... VLSI designs is a plus. * Experience with gate level simulation, power verification, reset ...
Design Verification Engineer
Santa Clara, UT · On-site
$60K - $148.50K/yr
Design Verification Engineer City: Santa Clara State/Province: California Posting Start Date: 5/20 ... VLSI Physical Place and Route. Experience: 5-8 Years. The expected compensation for this role ...
Design Verification Engineer
Santa Clara, UT · On-site
$60K - $148.50K/yr
Design Verification Engineer City: Santa Clara State/Province: California Posting Start Date: 5/20 ... VLSI Physical Place and Route. Experience: 5-8 Years. The expected compensation for this role ...
Silicon Design Verification Engineer
San Jose, CA · Hybrid
$159.70K - $195K/yr
The Verification Engineering team furthers and encourages continuous technical innovation to ... VLSI designs is a plus. * Experience with gate level simulation, power verification, reset ...
Silicon Design Verification Engineer
San Jose, CA · Hybrid
$159.70K - $195K/yr
The Verification Engineering team furthers and encourages continuous technical innovation to ... VLSI designs is a plus. * Experience with gate level simulation, power verification, reset ...
Silicon Design Verification Engineer
Austin, TX · On-site
$106.47K/yr
The Verification Engineering team furthers and encourages continuous technical innovation to ... VLSI designs is a plus. * Experience with gate level simulation, power verification, reset ...
Silicon Design Verification Engineer
Austin, TX · On-site
$106.47K/yr
The Verification Engineering team furthers and encourages continuous technical innovation to ... VLSI designs is a plus. * Experience with gate level simulation, power verification, reset ...
Digital Verification Engineer I
Austin, TX · Hybrid
$84K - $156K/yr
Support automated testing and verification flows through C programming and scripting. * Analyze ... Understanding ofdigital design fundamentals, computer architecture, VLSI concepts, or embedded ...
Digital Verification Engineer I
Austin, TX · Hybrid
$84K - $156K/yr
Support automated testing and verification flows through C programming and scripting. * Analyze ... Understanding ofdigital design fundamentals, computer architecture, VLSI concepts, or embedded ...
Design Verification Engineer (San Francisco)
$158.40K - $193.30K/yr
They seek skilled Verification Engineers or Chip Designers with substantial experience in VLSI front-end design flows, especially UVM, to work closely with ML and software teams. In this role, you ...
Design Verification Engineer (San Francisco)
$158.40K - $193.30K/yr
They seek skilled Verification Engineers or Chip Designers with substantial experience in VLSI front-end design flows, especially UVM, to work closely with ML and software teams. In this role, you ...
Vlsi Verification Engineer information
See salary details
$80K - $91.2K
1% of jobs
$91.2K - $102.5K
1% of jobs
$102.5K - $113.7K
1% of jobs
$113.7K - $124.9K
1% of jobs
$131.5K is the 25th percentile. Wages below this are outliers.
$124.9K - $136.1K
35% of jobs
The median wage is $138.3K / yr.
$136.1K - $147.4K
54% of jobs
$147.4K - $158.6K
1% of jobs
$158.6K - $169.8K
1% of jobs
$169.8K - $181K
2% of jobs
$181K - $192.3K
1% of jobs
$192.3K - $203.5K
1% of jobs
$80K
$142.6K
$203.5K
How much do vlsi verification engineer jobs pay per year?
What is a VLSI Verification Engineer job?
What are the key skills and qualifications needed to thrive in the Vlsi Verification Engineer position, and why are they important?
What are the typical daily responsibilities of a VLSI Verification Engineer?

Full-time
Posted 18 days ago
Hewlett Packard Enterprise rating
8.3
Based on 23 frontline employees who took The Breakroom Quiz
31st of 137 rated electronics manufacturers
Job description
Who We Are:
Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.Our culture thrives onfinding new and better ways to accelerate what's next.We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs.We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you.Open up opportunities with HPE.
Job Description:
Job DescriptionResponsibilities
- Provide leadership and direction for a team responsible for all phases ofpresilicon design verification, including verification planning, testbench development, coverage closure, regression management, and signoff reviews.
- Define, own, and evolvedesign verification methodology, ensuring consistent, highquality verification practices across block, subsystem, and fullchip scopes.
- Ensure development of robustSystemVerilog/UVMbased environments, including stimulus, scoreboards, checkers, assertions, and functional coverage.
- Drive regression health, failure triage, rootcause isolation, and closure of design issues in close collaboration with logic design and architecture teams.
- Manage project deliverables, schedules, and staffing to meet program milestones and quality goals.
- Recruit, mentor, and develop engineers; set performance expectations and support career growth across junior through senior levels.
- Identify and drive opportunities for process improvement, reuse, automation, and efficiency in verification workflows.
- Communicate verification status, risks, and readiness clearly to management and crossfunctional partners.
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
- Typically10+ years of experience in VLSI design verification, with strong handson background in presilicon DV.
- Strong understanding ofSystemVerilog and UVMbased verification methodologies.
- Demonstratedtechnical leadershipin design verification. (e.g., DV technical lead, block or project verification owner)
- Ability to lead engineers through influence, technical credibility, mentorship, and clear communication.
- Experience with verification planning, coveragedriven verification, regression management, and signoff readiness.
- Proficiency with DV workflows using industry EDA simulation tools.
- Strong analytical and problemsolving skills.
- Excellent written and verbal communication skills.
- Ability to operate effectively in a multisite, crossfunctional engineering environment.
- Previous peoplemanagement experience, including hiring, coaching, and performance management.
- Direct experience withSynopsys VCSlargescale regression execution, triage workflows, and performance/throughput optimization.
- Familiarity with GitHub Enterprise Cloud development workflows and AI tools is a plus.
- Familiarity with highperformance networking, Ethernet, SERDES, PCIe, or HPC/AI systems is a plus.
- Experience improving verification efficiency through automation, reuse, or methodology refinement.
What We Can Offer You:
Health & Wellbeing
We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
Personal & Professional Development
We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have - whether you want to become a knowledge expert in your field or apply your skills to another division.
Unconditional Inclusion
We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.
Let's Stay Connected:
Follow @HPECareers on Instagram to see the latest on people, culture and tech at HPE.
Job:
EngineeringJob Level:
Manager_1"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.- United States of America: Annual Salary USD 142,000 - 270,000 in Colorado // 135,000 - 310,500 in Minnesota & Wisconsin
The listed salary range reflects base salary. Variable incentives may also be offered."
Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html
The estimated job application period closure is May 15 2026; this timeline is provided for transparency and internal planning purposes.HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: Equal Employment Opportunity.
Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.
HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.
No Fees Notice & Recruitment Fraud Disclaimer
It has come to HPE's attention that there has been an increase in recruitment fraud whereby scammer impersonate HPE or HPE-authorized recruiting agencies and offer fake employment opportunities to candidates. These scammers often seek to obtain personal information or money from candidates.
Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendorswill never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process.The credentials of any hiring agency that claims to be working with HPE for recruitment of talent should be verified by candidates and candidates shall be solely responsible to conduct such verification. Any candidate/individual who relies on the erroneous representations made by fraudulent employment agencies does so at their own risk, and HPE disclaims liability for any damages or claims that may result from any such communication.
What Hewlett Packard Enterprise employees say
Pay
Hours and flexibility
Workplace
Get the full story on Breakroom
About Hewlett Packard Enterprise
Sourced by ZipRecruiter
Industry
It services
Company size
10,000+ Employees
Headquarters location
Spring, TX, US
Year founded
2015