VLSI Verification Engineer Location: Santa Clara, CA Duration 6 Month Contract Verification engineers - OVM/UVM is Mandatory CPU subsystem/DDR/Modem verification Additional Information All your ...
VLSI Verification Engineer Location: Santa Clara, CA Duration 6 Month Contract Verification engineers - OVM/UVM is Mandatory CPU subsystem/DDR/Modem verification Additional Information All your ...
ASIC Verification Engineer
Austin, TX · On-site
In depth knowledge in VLSI verification flow, languages and concepts. * Experience in data path or ... Debug the functionality with design engineers. * Perform coverage collection and follow the ...
ASIC Verification Engineer
Austin, TX · On-site
In depth knowledge in VLSI verification flow, languages and concepts. * Experience in data path or ... Debug the functionality with design engineers. * Perform coverage collection and follow the ...
ASIC Senior Verification Engineer
Austin, TX · On-site
In depth knowledge in VLSI verification flow, languages and concepts. * Experience in data path or ... Debug the functionality with design engineers. * Perform coverage collection and follow the ...
ASIC Senior Verification Engineer
Austin, TX · On-site
In depth knowledge in VLSI verification flow, languages and concepts. * Experience in data path or ... Debug the functionality with design engineers. * Perform coverage collection and follow the ...
ASIC verification engineer This role has been designed as ''Onsite' with an expectation that you ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
ASIC verification engineer This role has been designed as ''Onsite' with an expectation that you ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
Lead, mentor, and manage a team of verification engineers to meet project milestones and ... In-depth knowledge of VLSI verification flows , concepts, methodologies and interfaces with ...
Lead, mentor, and manage a team of verification engineers to meet project milestones and ... In-depth knowledge of VLSI verification flows , concepts, methodologies and interfaces with ...
ASIC verification engineer
Sunnyvale, CA · On-site
ASIC verification engineer This role has been designed as ''Onsite' with an expectation that you ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
ASIC verification engineer
Sunnyvale, CA · On-site
ASIC verification engineer This role has been designed as ''Onsite' with an expectation that you ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
ASIC verification engineer
Sunnyvale, CA · On-site
ASIC verification engineer This role has been designed as ''Onsite' with an expectation that you ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
ASIC verification engineer
Sunnyvale, CA · On-site
ASIC verification engineer This role has been designed as ''Onsite' with an expectation that you ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
ASIC verification engineer
Sunnyvale, CA · On-site
ASIC verification engineer This role has been designed as ''Onsite' with an expectation that you ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
ASIC verification engineer
Sunnyvale, CA · On-site
ASIC verification engineer This role has been designed as ''Onsite' with an expectation that you ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
ASIC design/verification engineer This role has been designed as 'Hybrid' with an expectation that ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
ASIC design/verification engineer This role has been designed as 'Hybrid' with an expectation that ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
ASIC design/verification engineer This role has been designed as 'Hybrid' with an expectation that ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
ASIC design/verification engineer This role has been designed as 'Hybrid' with an expectation that ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
ASIC design/verification engineer
Durham, NC · On-site
ASIC design/verification engineer This role has been designed as 'Hybrid' with an expectation that ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
ASIC design/verification engineer
Durham, NC · On-site
ASIC design/verification engineer This role has been designed as 'Hybrid' with an expectation that ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
ASIC / VLSI Engineers
Milpitas, CA · On-site
Design Verification Engineer Compensation up to $225K DOE + strong benefits + long-term project stability. What You Need (All Roles) * 8+ years of pre-silicon ASIC / VLSI experience * Strong ...
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ASIC / VLSI Engineers
Milpitas, CA · On-site
Design Verification Engineer Compensation up to $225K DOE + strong benefits + long-term project stability. What You Need (All Roles) * 8+ years of pre-silicon ASIC / VLSI experience * Strong ...
Design Verification Engineer
Irvine, CA · On-site
$146K - $178K/yr
Company Description Insilico is an End-to-End specialized VLSI, Embedded Design & Software services ... Job Title: Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High ...
Design Verification Engineer
Irvine, CA · On-site
$146K - $178K/yr
Company Description Insilico is an End-to-End specialized VLSI, Embedded Design & Software services ... Job Title: Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High ...
ASIC design/verification engineer This role has been designed as 'Hybrid' with an expectation that ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
ASIC design/verification engineer This role has been designed as 'Hybrid' with an expectation that ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
Principal ASIC Verification Engineer This role has been designed as 'Hybrid' with an expectation ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
Principal ASIC Verification Engineer This role has been designed as 'Hybrid' with an expectation ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
Verification Engineer
Englewood, CO · Hybrid
$130K - $200K/yr
What you will be doing * Plan & implement UVM verification environments developing tests ... VLSI Engineer, Location: Englewood, CO - 80113
Verification Engineer
Englewood, CO · Hybrid
$130K - $200K/yr
What you will be doing * Plan & implement UVM verification environments developing tests ... VLSI Engineer, Location: Englewood, CO - 80113
Design Verification Engineer
Irvine, CA · On-site
$146K - $178K/yr
Company Description Insilico is an End-to-End specialized VLSI, Embedded Design & Software services ... Job Title: Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High ...
Design Verification Engineer
Irvine, CA · On-site
$146K - $178K/yr
Company Description Insilico is an End-to-End specialized VLSI, Embedded Design & Software services ... Job Title: Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High ...
Principal ASIC Verification Engineer This role has been designed as 'Hybrid' with an expectation ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
Principal ASIC Verification Engineer This role has been designed as 'Hybrid' with an expectation ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
Verification Engineer
Englewood, CO · Hybrid
$130K - $200K/yr
What you will be doing * Plan & implement UVM verification environments developing tests ... VLSI Engineer, Location: Englewood, CO - 80113
Verification Engineer
Englewood, CO · Hybrid
$130K - $200K/yr
What you will be doing * Plan & implement UVM verification environments developing tests ... VLSI Engineer, Location: Englewood, CO - 80113
Principal ASIC Verification Engineer This role has been designed as 'Hybrid' with an expectation ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
Principal ASIC Verification Engineer This role has been designed as 'Hybrid' with an expectation ... Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems.
Temporary Vlsi Verification Engineer information
See salary details
$80K - $91.2K
1% of jobs
$91.2K - $102.5K
1% of jobs
$102.5K - $113.7K
1% of jobs
$113.7K - $124.9K
1% of jobs
$131.5K is the 25th percentile. Wages below this are outliers.
$124.9K - $136.1K
35% of jobs
The median wage is $138.3K / yr.
$136.1K - $147.4K
54% of jobs
$147.4K - $158.6K
1% of jobs
$158.6K - $169.8K
1% of jobs
$169.8K - $181K
2% of jobs
$181K - $192.3K
1% of jobs
$192.3K - $203.5K
1% of jobs
$80K
$142.6K
$203.5K
How much do temporary vlsi verification engineer jobs pay per year?
As of Jul 11, 2026, the average yearly pay for temporary vlsi verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.
What are the key skills and qualifications needed to thrive as a Temporary VLSI Verification Engineer, and why are they important?
To thrive as a Temporary VLSI Verification Engineer, you need a solid background in digital design, computer architecture, and verification methodologies, usually supported by a degree in electrical or computer engineering. Proficiency with verification tools such as SystemVerilog, UVM, simulation environments, and scripting languages (e.g., Python, Perl) is typically required. Strong analytical thinking, attention to detail, and effective teamwork are soft skills that set candidates apart. These skills and qualities are critical to ensure high-quality silicon designs, timely project delivery, and reliable collaboration in complex engineering environments.
What are Temporary VLSI Verification Engineers?
Temporary VLSI Verification Engineers are professionals hired on a contract or short-term basis to test and validate the design and functionality of Very Large Scale Integration (VLSI) chips and systems. They use specialized tools and methodologies to ensure that integrated circuits meet design specifications and work as intended. Their work involves creating and running verification environments, debugging, and collaborating with design teams to identify and resolve issues. Temporary positions allow companies to scale engineering resources during peak project phases or to fill gaps in their permanent workforce.
What are some common challenges faced by a Temporary VLSI Verification Engineer, and how can they be overcome?
As a Temporary VLSI Verification Engineer, one common challenge is quickly familiarizing yourself with complex design architectures and proprietary verification environments within a limited timeframe. Adapting to various verification methodologies and tools can also be demanding, especially when joining ongoing projects. To overcome these challenges, it's important to proactively communicate with team members, leverage documentation, and prioritize learning the verification processes and scripting languages used by the team. Being adaptable and asking clarifying questions early on can help ensure a smooth integration and effective contribution.
What cities are hiring for Temporary Vlsi Verification Engineer jobs? Cities with the most Temporary Vlsi Verification Engineer job openings:
What are the most commonly searched types of Vlsi Verification Engineer jobs? The most popular types of Vlsi Verification Engineer jobs are:
What states have the most Temporary Vlsi Verification Engineer jobs? States with the most job openings for Temporary Vlsi Verification Engineer jobs include:
$159K/yr
Contractor
Posted 22 days ago
Job description
Company Description
EROS Technologies was founded with a simple motive of offering the clients exactly what they want, how they want and when they want it. By leveraging for its clients its technological edge and right-sourcing advantage, EROS in a short period of time has grown to become one of the most trusted strategic technology partners. Treating every client as the top priority, we customize our solutions and services to align with the unique needs of each client.
Job Description
Job Title: VLSI Verification Engineer
Location: Santa Clara, CA
Duration 6 Month Contract
Job description:
Verification engineers - OVM/UVM is Mandatory
CPU subsystem/DDR/Modem verification
Additional Information
All your information will be kept confidential according to EEO guidelines.
About Eros Technologies
Sourced by ZipRecruiter
We create a culture that inspires us to work smart, together. Experience Eros is dedicated to delivering services to all our Fortune 100 to Fortune 500, SME, and Enterprise customers in the USA, Canada, and India. Eros Technologies is a leading Global Consulting and IT services company, offering a wider variety of solutions customized to the needs of demanding industries and diversified business environments. We help clients move forward in every part of their businesses, from strategic planning to day-to-day operations by enhancing our consulting and outsourcing expertise with alliances and other capabilities. Eros can mobilize the right people, skills, and technologies to help its clients improve their performances. We create Solutions with the aim of increasing your organization’s efficiency, productivity, and profits.
Industry
Human resources consulting services
Company size
1,001 - 5,000 Employees
Headquarters location
Lewes, DE, US
Year founded
2015