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Virtual Reception Jobs in California (NOW HIRING)

TylSemi

Principal PCIe Subsystem RTL lead

San Jose, CA · On-site

$159K - $164K/yr

TLP reception, integrity checking, header classification, routing decisions, and handoff to downstream subsystems. * Own the Virtual Channel and flow-control architecture, ensuring fair arbitration ...

Alliance Animal Health

Veterinary Receptionist

Los Angeles, CA · On-site

$19/hr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Maintain the visual appeal of the hospital reception area, greet and welcome clients and patients ... of virtual and hands on, interactive training and continuing development. Qualifications We're ...

Alliance Animal Health

Veterinary Receptionist

Los Angeles, CA · On-site

$19/hr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Maintain the visual appeal of the hospital reception area, greet and welcome clients and patients ... of virtual and hands on, interactive training and continuing development. Qualifications We're ...

Tricehealthcare

Receptionist

Sacramento, CA · On-site

$17.25 - $22.50/hr

... the reception area • General administrative support to center activities • Classroom ... Does the position allow for the worker to be virtual/remote? : No * Shore Options Available for ...

Pain & Rehabilitative Consultants Medical Group

Be Seen First

Clinic Support Specialist II

Emeryville, CA · On-site

$22 - $29/hr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

... welcoming reception area. plays a key role in supporting clinical operations and ensuring a ... for virtual appointments. * Oversee assigned medical equipment and ensure proper operation ...

Prosperous Health

Office Manager

Agoura Hills, CA · On-site

$16 - $30/hr

  • Medical

  • Dental

  • Vision

  • PTO

Prosperous Health Virtual Care - Statewide telehealth behavioral health program Position Summary ... Keep reception and common areas clean, organized, and welcoming * Assist with data entry, scanning ...

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Virtual Reception information

What does a virtual receptionist do?

A virtual receptionist manages incoming calls, emails, and messages for a business remotely. They often use communication tools like phone systems and scheduling software to handle client inquiries, schedule appointments, and provide customer service from a remote location.

What is the difference between Virtual Reception vs Virtual Assistant?

AspectVirtual ReceptionVirtual Assistant
Primary RoleHandling incoming calls, greeting clients, managing front-desk tasks remotelyPerforming a variety of administrative tasks, including scheduling, email management, research
Skills & CertificationsExcellent communication, customer service, basic tech skillsOrganizational skills, communication, proficiency in office software
Work EnvironmentRemote, often client-facing, focused on reception dutiesRemote, versatile, supporting multiple business functions
Industry UsageCommon in customer service, hospitality, healthcareCommon across various industries like marketing, real estate, admin support

While both roles are remote and involve administrative skills, a Virtual Reception primarily manages incoming calls and front-desk tasks, focusing on customer interaction. A Virtual Assistant handles a broader range of administrative duties, supporting overall business operations. Understanding these differences helps employers and job seekers find the right fit for their needs.

What are the most commonly searched types of Reception jobs in California?

The most popular types of Reception jobs in California are:

What cities in California are hiring for Virtual Reception jobs?

Cities in California with the most Virtual Reception job openings:

Virtual Reception jobs near you
Infographic showing various Virtual Reception job openings in California as of August 2026, with employment types broken down into 1% As Needed, 76% Full Time, 17% Part Time, 2% Temporary, and 4% Contract. Highlights an 75% Physical, 3% Hybrid, and 22% Remote job distribution.

Principal PCIe Subsystem RTL lead

TylSemi

San Jose, CA • On-site

$159K - $164K/yr

Full-time

Re-posted yesterday

Job description

We are looking for a Principal PCIe Sub-system Front-end RTL lead for next generation chiplet based SoCs for High-performance Compute and AI silicon .
What You'll Do
  • Own the PCIe subsystem microarchitecture from the PHY interface through the MAC and Transaction Layer, defining the internal block boundaries, data paths, and control interfaces.
  • Lead the integration of third-party PCIe controller and PHY hard IP, including wrapper RTL that adds mode selection, telemetry hooks, and bridging logic to the chiplet's internal fabric.
  • Define and implement the bifurcation and lane-configuration logic, ensuring all supported lane-width configurations operate correctly across the full range of operating modes.
  • Specify and drive implementation of the Transaction Layer pipeline: TLP reception, integrity checking, header classification, routing decisions, and handoff to downstream subsystems.
  • Own the Virtual Channel and flow-control architecture, ensuring fair arbitration and back-pressure handling across all traffic classes.
  • Define the integration interface to the PCIe subsystem such asTLP-to-flit adaptation, flow-control mapping, and error handling at the boundary.
  • Collaborate with the management firmware team to define the PCIe register map, mode-select interface, and run-time telemetry structures exposed to the on-chip management processor.
  • Work with the Physical Design Lead to meet timing closure requirements for the PCIe subsystem, including MAC-PHY interface timing, reset sequencing, and floorplan constraints.
  • Hold the PCIe performance budget for each operating mode: bandwidth efficiency, latency through the Transaction Layer, and error recovery overhead.
  • Define the PCIe power management architecture - link state transitions, ASPM policy, and integration with the chiplet-level power coordination scheme.
  • Lead PCIe silicon bring-up planning: define bringup sequence, debug instrumentation requirements, loopback modes, and the hand-off criteria for production readiness.
  • Mentor and guide RTL design engineers responsible for PCIe subsystem implementation, providing architectural guidance and RTL review.
  • Partner with the DV team to define the PCIe UVM verification plan, coverage model, and protocol-checker requirements.
  • Serve as the technical point of contact for PCIe-related customer integration questions, supporting anchor customer engagements on interface bring-up and interoperability.
  • Author and maintain the PCIe subsystem micro-architecture specification, keeping it current through RTL implementation and sign-off.

What We're Looking For
  • 10+ years of digital IC design experience, with at least 4 years focused on PCIe subsystem design or integration at the block-lead or module-owner level.
  • Deep expertise in PCIe architecture: Transaction Layer, Data Link Layer, Physical Layer, TLP structure, flow control, Virtual Channels, and error handling.
  • Hands-on experience integrating PCIe hard IP (controller and/or SerDes PHY) into production SoC or chiplet designs, including wrapper RTL, reset sequencing, and PnR constraints.
  • Background in SR-IOV, multi-function device configuration, or host software driver interaction at the hardware level.
  • Strong SystemVerilog RTL skills: able to write, review, and own production RTL for complex pipelined state machines, FIFOs, arbiters, and control logic.
  • CXL 1.1/2.0 or 3.0 protocol knowledge, particularly CXL.io and CXL.mem transaction handling built on the PCIe fabric.
  • Solid understanding of PCIe PHY-MAC interface protocols and timing requirements,
  • Experience with PCIe compliance testing and PCI-SIG certification process - understanding of test requirements, common failure modes, and debug methodology.
  • Familiarity with PCIe power management, L0s/L1 state machines, state transitions etc.
  • Competency in multi-clock-domain design: async FIFO, CDC synchronizers, and clock crossing at the PCIe-to-internal-fabric boundary.
  • BS/MS in Electrical Engineering, Computer Engineering, or equivalent.

Good To Have
  • Experience with UCIe or another die-to-die protocol at the PCIe TLP adaptation layer - mapping TLPs to a flit-based D2D transport.
  • Prior experience with protocol bridging or gearbox designs that span multiple PCIe generations.
  • Familiarity with PCIe IP integration, including customization and support engagement.
  • Experience at an advanced-node (7 nm or below) tape-out, particularly with the timing closure and floorplan considerations for designs.

Location
Hybrid/On-site - San Jose, CA / Remote -USA
About TylSemi, Inc.
The Opportunity
The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?
That's what we solve. TylSemi builds the chiplet infrastructure IP - the IO, power delivery, and interconnect building blocks - that makes AI/HPC systems actually work at scale.
This isn't a nice-to-have. It's the critical path.
Why Now
The Market Window
The semiconductor industry is going through its biggest architectural shift in 40 years:
• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI - they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.
Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.
Culture & Team: How We Work
No Politics, No Bureaucracy
There are no layers, no approval chains, no corporate theater.
• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.
Remote-Friendly, Global Team
• US team: Bay Area preferred, but we hire the best people regardless of location
• India team: Building a world-class design center in Bangalore
Move Fast, Ship Real Products
We're not a research project. We have paying customers, committed capital, and aggressive timelines.
This is a company, not a lifestyle business. We're building to win.
What We Value
• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
• Bias for action. We move fast. Analysis paralysis doesn't fly here.
• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards. We don't care about titles or politics. We care about results.
The Ask
If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.
We're asking you to walk away from that and bet on us.
Here's why you should:
• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.
• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.
• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.
This is the bet. Join us and build something that matters.
Or stay comfortable. No judgment.
But if you're the kind of person who wants to take the shot, we'd love to talk.
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