Senior FPGA Design Engineer
$116K - $160K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
$116K - $160K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
$116K - $160K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
$116K - $160K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel Foundry Services customers on PDKs through ASIC design implementation flows and to perform ASIC physical ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel Foundry Services customers on PDKs through ASIC design implementation flows and to perform ASIC physical ...
Senior FPGA Design Engineer
Tucson, AZ · On-site
$116K - $160K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
Tucson, AZ · On-site
$116K - $160K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel Foundry Services customers on PDKs through ASIC design implementation flows and to perform ASIC physical ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel Foundry Services customers on PDKs through ASIC design implementation flows and to perform ASIC physical ...
Senior Design Verification Engineer
$176K - $264K/yr
As a Design Verification Engineer, you will be part of a verification team responsible for the full cycle of RTL verification for FPGA and ASIC designs. You will be responsible for: * Design ...
Senior Design Verification Engineer
$176K - $264K/yr
As a Design Verification Engineer, you will be part of a verification team responsible for the full cycle of RTL verification for FPGA and ASIC designs. You will be responsible for: * Design ...
We are seeking an experienced, self-motivated, and passionate engineer to lead, architect, and ... RTL Design and Implementation: Use Verilog and SystemVerilog to design digital blocks, subsystems ...
We are seeking an experienced, self-motivated, and passionate engineer to lead, architect, and ... RTL Design and Implementation: Use Verilog and SystemVerilog to design digital blocks, subsystems ...
If you are an engineer who enjoys equally RTL and low-level C, this team will give you the ... Familiarity with RTL design using Verilog or SystemVerilog * Understanding of digital logic design ...
If you are an engineer who enjoys equally RTL and low-level C, this team will give you the ... Familiarity with RTL design using Verilog or SystemVerilog * Understanding of digital logic design ...
If you are an engineer who enjoys equally RTL and low-level C, this team will give you the ... Familiarity with RTL design using Verilog or SystemVerilog * Understanding of digital logic design ...
If you are an engineer who enjoys equally RTL and low-level C, this team will give you the ... Familiarity with RTL design using Verilog or SystemVerilog * Understanding of digital logic design ...
Senior Design Verification Engineer with Security Clearance
Tempe, AZ · On-site
$176K - $264K/yr
As a Design Verification Engineer, you will be part of a verification team responsible for the full cycle of RTL verification for FPGA and ASIC designs. You will be responsible for: * Design ...
Senior Design Verification Engineer with Security Clearance
Tempe, AZ · On-site
$176K - $264K/yr
As a Design Verification Engineer, you will be part of a verification team responsible for the full cycle of RTL verification for FPGA and ASIC designs. You will be responsible for: * Design ...
Principal FPGA/ASIC Engineer - Level 3
$79K - $118K/yr
The Principal FPGA/ASIC Engineer will be responsible for research, requirements analysis and ... Proficiency in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
Principal FPGA/ASIC Engineer - Level 3
$79K - $118K/yr
The Principal FPGA/ASIC Engineer will be responsible for research, requirements analysis and ... Proficiency in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
FPGA VHDL Design Engineer US Citizenship required
Tucson, AZ · On-site
$116K - $160K/yr
We have a PERM position in sunny Tucson, AZ for an ASIC FPGA Designer. There are several positions ... Engineer (ASIC Design) FPGA ASIC design experience required. Knowledge and experience including ...
FPGA VHDL Design Engineer US Citizenship required
Tucson, AZ · On-site
$116K - $160K/yr
We have a PERM position in sunny Tucson, AZ for an ASIC FPGA Designer. There are several positions ... Engineer (ASIC Design) FPGA ASIC design experience required. Knowledge and experience including ...
FPGA VHDL Design Engineer US Citizenship required
Tucson, AZ · On-site
$116K - $160K/yr
We have a PERM position in sunny Tucson, AZ for an ASIC FPGA Designer. There are several positions ... Engineer (ASIC Design) FPGA ASIC design experience required. Knowledge and experience including ...
FPGA VHDL Design Engineer US Citizenship required
Tucson, AZ · On-site
$116K - $160K/yr
We have a PERM position in sunny Tucson, AZ for an ASIC FPGA Designer. There are several positions ... Engineer (ASIC Design) FPGA ASIC design experience required. Knowledge and experience including ...
Senior FPGA Design Engineer with Security Clearance
Tucson, AZ · On-site
$114K - $157K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer with Security Clearance
Tucson, AZ · On-site
$114K - $157K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior IP Design Engineer
Chandler, AZ · Hybrid
$161K - $218K/yr
Developing RTL, fixing bugs, performing design checks and generating of implementation constraints ... Computer Engineering or a similar related field and experience working in design of complex ...
New
Senior IP Design Engineer
Chandler, AZ · Hybrid
$161K - $218K/yr
Developing RTL, fixing bugs, performing design checks and generating of implementation constraints ... Computer Engineering or a similar related field and experience working in design of complex ...
New
Advanced ASIC FPGA Design Engineer for Crypto and Cross Domain Solutions
Scottsdale, AZ · On-site
$135K - $150K/yr
Strong proficiency in VHDL and/or Verilog/SystemVerilog for synthesizable RTL design * Hands-on ... General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions ...
Advanced ASIC FPGA Design Engineer for Crypto and Cross Domain Solutions
Scottsdale, AZ · On-site
$135K - $150K/yr
Strong proficiency in VHDL and/or Verilog/SystemVerilog for synthesizable RTL design * Hands-on ... General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions ...
Advanced ASIC FPGA Design Engineer for Crypto and Cross Domain Solutions
Scottsdale, AZ · On-site
$135K - $150K/yr
Strong proficiency in VHDL and/or Verilog/SystemVerilog for synthesizable RTL design * Hands-on ... Company Overview General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high ...
Advanced ASIC FPGA Design Engineer for Crypto and Cross Domain Solutions
Scottsdale, AZ · On-site
$135K - $150K/yr
Strong proficiency in VHDL and/or Verilog/SystemVerilog for synthesizable RTL design * Hands-on ... Company Overview General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high ...
Principal IC Design Engineer
Chandler, AZ · On-site
$145K - $185K/yr
The Principal IC Design Engineer will architect innovative circuits to solve electronic system ... Support ASIC qualification, including hardware and software development, and interface with end ...
Principal IC Design Engineer
Chandler, AZ · On-site
$145K - $185K/yr
The Principal IC Design Engineer will architect innovative circuits to solve electronic system ... Support ASIC qualification, including hardware and software development, and interface with end ...
As a Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
As a Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
As a Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
As a Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Temporary Asic Rtl Design Engineer information
What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?
| Aspect | Temporary Asic Rtl Design Engineer | Temporary FPGA Design Engineer |
|---|---|---|
| Primary Focus | Designing RTL code for ASIC chips | Designing FPGA logic and configurations |
| Skills & Certifications | Verilog/VHDL, ASIC design flow, simulation tools | Verilog/VHDL, FPGA development tools, synthesis |
| Work Environment | Semiconductor companies, ASIC design teams | FPGA development labs, prototyping environments |
| Industry Usage | Used in high-volume chip manufacturing | Used for prototyping, testing, and low-volume products |
Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.
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$116K - $160K/yr
Full-time
Medical, Dental, Vision, Life, Retirement, PTO
Posted 26 days ago
Raytheon rating
9.1
Based on 95 frontline employees who took The Breakroom Quiz
3rd of 527 rated manufacturers
Job description
Date Posted:
2026-05-14Country:
United States of AmericaLocation:
US-AZ-TUCSON-M02 ~ 1151 E Hermans Rd ~ BLDG M02Position Role Type:
OnsiteU.S. Citizen, U.S. Person, or Immigration Status Requirements:
Active and transferable U.S. government issued security clearance is required prior to start date. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearanceSecurity Clearance Type:
Secret - CurrentSecurity Clearance Status:
Ability to obtain INTERIM U.S. government issued security clearance is required prior to start dateAt RTX, the world largest aerospace and defense company, 185,000 great minds are united by purpose and inspired to make a difference solving the world’s most complex problems. With our three market leading businesses, world-class operations and investments in research and development, we offer capabilities and opportunity no one else can. Together, we push the boundaries of known science and find new ways to connect and protect our world.
Raytheon brings the strength of more than 100 years of experience and renowned engineering expertise to meet the needs of today’s mission and stay ahead of tomorrow’s threat. We deliver solutions that help our nation and allies defend freedoms and deter aggression, creating a safer, more secure world. Join us and help shape the future of aerospace and defense.
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device families including: Xilinx, Altera, and Microsemi. Designs are implemented using VHDL for the following applications: gigabit serial interfaces, Radio Frequency (RF) and Electro-Optical (EO) DSP, controls, data links, embedded processing and processor interfaces.
Designers work with circuit card designers and systems engineers to develop requirements, architect new parts, collaborative modeling of algorithms, partition and perform code development, simulation, and place and route. Designs are verified against requirements using both directed test and constrained random methodologies. Design support is expected from requirements definition through integration and test. Design documentation and configuration management are required.
What You Will Do
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Design and deliver production quality FPGA releases from initial proof of concept up to production
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Architect FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS)
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Translate system level requirements into FPGA requirements
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Design and code in VHDL for reliability and maintainability
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Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage
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Help drive projects and execute program schedules on time and budget
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Create complete documentation including requirements, verification plan, and user’s guides
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Lead small teams and mentor junior engineers
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Support internal and external technical reviews
Qualifications You Must Have
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Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 5 years of prior relevant experience
Experience with at least one of the following:
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FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using SystemVerilog coding
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Working with Xilinx or Microsemi devices and associated flow tools
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Delivering FPGA/ASIC solutions for system-level applications
Qualifications We Prefer
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FPGA/ASIC design experience in one or more of the following areas:
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Hands-on experience with integration and debugging of FPGA/ASIC devices
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Radar processing techniques
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Image processing techniques for visual and infrared sensors
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Embedded systems design using ARM, Microblaze, or Nios processors
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Gigabit serial interfaces and multi-gigabit transceivers (MGTs)
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Constrained random verification in UVM using System Verilog
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Verification utilizing emulation platforms, such as Veloce
What We Offer
Our values drive our actions, behaviors, and performance with a vision for a safer, more connected world. At RTX we value: Safety, Trust, Respect, Accountability, Collaboration, and Innovation.
Relocation
9/8 Schedule – every other Friday off!
Learn More & Apply Now!
This position is onsite work in Tucson, AZ: https://careers.rtx.com/global/en/raytheon-tucson,-az-location
Please consider the following role type definition as you apply for this role:
‒ Onsite: Employees who are working in Onsite roles will work primarily onsite. This includes all production and maintenance employees, as they are essential to the development of our products.
As part of our commitment to maintaining a secure hiring process, candidates may be asked to attend select steps of the interview process in-person at one of our office locations, regardless of whether the role is designated as on-site, hybrid or remote.
The salary range for this role is 86,800 USD - 165,200 USD. The salary range provided is a good faith estimate representative of all experience levels. RTX considers several factors when extending an offer, including but not limited to, the role, function and associated responsibilities, a candidate’s work experience, location, education/training, and key skills. Hired applicants may be eligible for benefits, including but not limited to, medical, dental, vision, life insurance, short-term disability, long-term disability, 401(k) match, flexible spending accounts, flexible work schedules, employee assistance program, Employee Scholar Program, parental leave, paid time off, and holidays. Specific benefits are dependent upon the specific business unit as well as whether or not the position is covered by a collective-bargaining agreement. Hired applicants may be eligible for annual short-term and/or long-term incentive compensation programs depending on the level of the position and whether or not it is covered by a collective-bargaining agreement. Payments under these annual programs are not guaranteed and are dependent upon a variety of factors including, but not limited to, individual performance, business unit performance, and/or the company’s performance. This role is a U.S.-based role. If the successful candidate resides in a U.S. territory, the appropriate pay structure and benefits will apply. RTX anticipates the application window closing approximately 40 days from the date the notice was posted. However, factors such as candidate flow and business necessity may require RTX to shorten or extend the application window.RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status, or any other applicable state or federal protected class. RTX provides affirmative action in employment for qualified Individuals with a Disability and Protected Veterans in compliance with Section 503 of the Rehabilitation Act and the Vietnam Era Veterans’ Readjustment Assistance Act.
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