You will own CPU focused test generator development and verification strategy, shaping how our out-of-order RISC-V CPUs are validated against complex ISA and microarchitectural behavior. This role is ...
You will own CPU focused test generator development and verification strategy, shaping how our out-of-order RISC-V CPUs are validated against complex ISA and microarchitectural behavior. This role is ...
Linux Kernel Architect
Santa Clara, CA · On-site
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
Linux Kernel Architect
Santa Clara, CA · On-site
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value ...
Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value ...
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
Lead Debug/Trace/Profiling Design Engineer
Boston, MA · On-site
$111K - $146K/yr
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
Lead Debug/Trace/Profiling Design Engineer
Boston, MA · On-site
$111K - $146K/yr
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
Linux Kernel Architect
Boston, MA · On-site
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
Linux Kernel Architect
Boston, MA · On-site
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
Power Management Design Engineer
Boston, MA · On-site
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
Power Management Design Engineer
Boston, MA · On-site
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
IP Design Architect
Austin, TX · On-site
Drive graphics, display, and/or RISC-V IP ideas from definition through modeling and architecture, to design and implementations, with participation in all stages. * Implement and evaluate ...
IP Design Architect
Austin, TX · On-site
Drive graphics, display, and/or RISC-V IP ideas from definition through modeling and architecture, to design and implementations, with participation in all stages. * Implement and evaluate ...
Linux Kernel Architect
Santa Clara, CA · On-site
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
Linux Kernel Architect
Santa Clara, CA · On-site
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
Lead Debug/Trace/Profiling Design Engineer
Austin, TX · On-site
$101K - $133K/yr
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
Lead Debug/Trace/Profiling Design Engineer
Austin, TX · On-site
$101K - $133K/yr
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
Linux Kernel Architect
Santa Clara, CA · On-site
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
Linux Kernel Architect
Santa Clara, CA · On-site
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data ...
Risc V information
See salary details
$15.63 - $18.75
2% of jobs
$18.75 - $21.88
9% of jobs
$24.94 is the 25th percentile. Wages below this are outliers.
$21.88 - $25
14% of jobs
$25 - $28.13
19% of jobs
The median wage is $29.14 / hr.
$28.13 - $31.25
18% of jobs
$31.25 - $34.38
13% of jobs
$34.47 is the 75th percentile. Wages above this are outliers.
$34.38 - $37.50
8% of jobs
$37.50 - $40.63
6% of jobs
$40.63 - $43.75
4% of jobs
$43.75 - $46.88
3% of jobs
$46.88 - $50
3% of jobs
$15
$31
$50
How much do risc v jobs pay per hour?
As of Sep 13, 2026, the average hourly pay for risc v in the United States is $31.52, according to ZipRecruiter salary data. Most workers in this role earn between $24.76 and $35.82 per hour, depending on experience, location, and employer.
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CPU Core Design Verification Test Generator Lead
Hybrid
Tenstorrent
Full-time
Re-posted 9 hours ago
Job description
At Tenstorrent, we build open, state of the art compute for real workloads and real developers.
You will own CPU focused test generator development and verification strategy, shaping how our out-of-order RISC-V CPUs are validated against complex ISA and microarchitectural behavior.Â
This role is hybrid, based out of Austin, TX or Santa Clara, CA.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You AreÂ
- You bring 8+ years in CPU design verification, test generation, or closely related CPU validation work.
- You have led development of test generators for x86, ARM, or RISC-V ISA environments.
- You understand CPU ISA behavior, privileged architecture, and high-performance out-of-order CPU microarchitecture.
- You are comfortable building tools, stimulus, and automation that scale verification across large CPU programs.
- You communicate clearly across design, DV, architecture, emulation, and post-silicon teams.
What We NeedÂ
- Lead development of CPU core-level test generators for high-performance out-of-order RISC-V cores.
- Own generator strategy, infrastructure, and methodology for ISA and microarchitectural verification in both pre-silicon and post-siliconÂ
- Develop directed and randomized stimulus that targets architectural corner cases, instruction interactions, and complex CPU behavior.
- Support RISC-V certification work, including test content, compliance flows, debug, and closure.
- Guide a small team of 4-5 engineers while staying hands-on with implementation, debug, and verification execution.
What You Will LearnÂ
- How Tenstorrent designs and validates high-performance RISC-V CPU cores and clusters.
- Techniques for scaling CPU test generator infrastructure across core, cluster, and chip-level environments.
- Ways to apply ISA-driven stimulus to complex CPU verification and debug workflows.
- Techniques for supporting RISC-V certification alongside internal verification requirements.
- How to scale coverage, debug, and generator methodology across multiple CPU programs within Tenstorrent's broader compute roadmap.