Excited by semiconductors, RISC-V, AI, and the process of turning cutting-edge ideas into products ... and deliverables. * Assist in gathering and analyzing data to support product decisions and ...
Excited by semiconductors, RISC-V, AI, and the process of turning cutting-edge ideas into products ... and deliverables. * Assist in gathering and analyzing data to support product decisions and ...
FPGA Digital Design and Verification Engineer-Contract
San Jose, CA · On-site
$100/hr
RISC-V design * Develop and maintain SystemVerilog/UVM-based verification environments for FPGA IPs ... * Assist in debugging RTL and verification failures, working closely with design engineers
FPGA Digital Design and Verification Engineer-Contract
San Jose, CA · On-site
$100/hr
RISC-V design * Develop and maintain SystemVerilog/UVM-based verification environments for FPGA IPs ... * Assist in debugging RTL and verification failures, working closely with design engineers
CPU Verification
Santa Clara, CA · On-site
$80 - $85/hr
Analyze coverage reports and assist in closing coverage gaps. * Automate regression and ... Exposure to RISC-V architecture. * Knowledge of interconnect protocols like AXI, ACE, or CHI.
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CPU Verification
Santa Clara, CA · On-site
$80 - $85/hr
Analyze coverage reports and assist in closing coverage gaps. * Automate regression and ... Exposure to RISC-V architecture. * Knowledge of interconnect protocols like AXI, ACE, or CHI.
With SiFive, the future of RISC-V has no limits. At SiFive, we are always excited to connect with ... SiFive is seeking a highly capable Executive Business Partner / Executive Assistant to the CTO & EV ...
With SiFive, the future of RISC-V has no limits. At SiFive, we are always excited to connect with ... SiFive is seeking a highly capable Executive Business Partner / Executive Assistant to the CTO & EV ...
Executive Business Partner / Executive Assistant to the CTO & EVP Engineering
Santa Clara, CA · On-site
With SiFive, the future of RISC-V has no limits. At SiFive, we are always excited to connect with ... SiFive is seeking a highly capable Executive Business Partner / Executive Assistant to the CTO & EV ...
Executive Business Partner / Executive Assistant to the CTO & EVP Engineering
Santa Clara, CA · On-site
With SiFive, the future of RISC-V has no limits. At SiFive, we are always excited to connect with ... SiFive is seeking a highly capable Executive Business Partner / Executive Assistant to the CTO & EV ...
Embedded Software Engineer with Security Clearance
$135.20K - $177.80K/yr
... ARM, RISC-V, NIOS, etc.) Develop and support standalone embedded applications Assist in RESTConf interface design and implementation Utilize emulation environments for testing and validation ...
Embedded Software Engineer with Security Clearance
$135.20K - $177.80K/yr
... ARM, RISC-V, NIOS, etc.) Develop and support standalone embedded applications Assist in RESTConf interface design and implementation Utilize emulation environments for testing and validation ...
Posting Details Position Details Position Type Tenure Track Working Title Assistant or Associate ... Knowledge and skills in RISC-V, ARM, and digital logic design using FPGAs with Verilog HDL are ...
Posting Details Position Details Position Type Tenure Track Working Title Assistant or Associate ... Knowledge and skills in RISC-V, ARM, and digital logic design using FPGAs with Verilog HDL are ...
Principal Design Verification Engineer
Austin, TX · On-site
$153K - $290K/yr
Analyze coverage reports and assist in closing coverage gaps. * Automate regression and ... Exposure to RISC-V architecture. * Knowledge of interconnect protocols like AXI, ACE, or CHI.
Principal Design Verification Engineer
Austin, TX · On-site
$153K - $290K/yr
Analyze coverage reports and assist in closing coverage gaps. * Automate regression and ... Exposure to RISC-V architecture. * Knowledge of interconnect protocols like AXI, ACE, or CHI.
Principal Design Verification Engineer
Richardson, TX · On-site
$153K - $265K/yr
Analyze coverage reports and assist in closing coverage gaps. * Automate regression and ... Exposure to RISC-V architecture. * Knowledge of interconnect protocols like AXI, ACE, or CHI.
Principal Design Verification Engineer
Richardson, TX · On-site
$153K - $265K/yr
Analyze coverage reports and assist in closing coverage gaps. * Automate regression and ... Exposure to RISC-V architecture. * Knowledge of interconnect protocols like AXI, ACE, or CHI.
Principal Design Verification Engineer
Richardson, TX · On-site
$153K - $265K/yr
Analyze coverage reports and assist in closing coverage gaps. * Automate regression and ... Exposure to RISC-V architecture. * Knowledge of interconnect protocols like AXI, ACE, or CHI.
Principal Design Verification Engineer
Richardson, TX · On-site
$153K - $265K/yr
Analyze coverage reports and assist in closing coverage gaps. * Automate regression and ... Exposure to RISC-V architecture. * Knowledge of interconnect protocols like AXI, ACE, or CHI.
Principal Design Verification Engineer
Austin, TX · On-site
$153K - $290K/yr
Analyze coverage reports and assist in closing coverage gaps. * Automate regression and ... Exposure to RISC-V architecture. * Knowledge of interconnect protocols like AXI, ACE, or CHI.
Principal Design Verification Engineer
Austin, TX · On-site
$153K - $290K/yr
Analyze coverage reports and assist in closing coverage gaps. * Automate regression and ... Exposure to RISC-V architecture. * Knowledge of interconnect protocols like AXI, ACE, or CHI.
Principal Design Verification Engineer
Austin, TX · On-site
$153K - $265K/yr
Analyze coverage reports and assist in closing coverage gaps. * Automate regression and ... Exposure to RISC-V architecture. * Knowledge of interconnect protocols like AXI, ACE, or CHI.
Principal Design Verification Engineer
Austin, TX · On-site
$153K - $265K/yr
Analyze coverage reports and assist in closing coverage gaps. * Automate regression and ... Exposure to RISC-V architecture. * Knowledge of interconnect protocols like AXI, ACE, or CHI.
Principal Design Verification Engineer
Austin, TX · On-site
$153K - $265K/yr
Analyze coverage reports and assist in closing coverage gaps. * Automate regression and ... Exposure to RISC-V architecture. * Knowledge of interconnect protocols like AXI, ACE, or CHI.
Principal Design Verification Engineer
Austin, TX · On-site
$153K - $265K/yr
Analyze coverage reports and assist in closing coverage gaps. * Automate regression and ... Exposure to RISC-V architecture. * Knowledge of interconnect protocols like AXI, ACE, or CHI.
Sr Principal CPU Verification Engineer
Austin, TX · On-site
$171K - $296K/yr
Analyze coverage reports and assist in closing coverage gaps. * Automate regression and ... Exposure to RISC-V architecture. * Knowledge of interconnect protocols like AXI, ACE, or CHI.
Sr Principal CPU Verification Engineer
Austin, TX · On-site
$171K - $296K/yr
Analyze coverage reports and assist in closing coverage gaps. * Automate regression and ... Exposure to RISC-V architecture. * Knowledge of interconnect protocols like AXI, ACE, or CHI.
Sr Principal Engineer CPU Verification
Austin, TX · On-site
$171K - $296K/yr
Analyze coverage reports and assist in closing coverage gaps. * Automate regression and ... Exposure to RISC-V architecture. * Knowledge of interconnect protocols like AXI, ACE, or CHI.
Sr Principal Engineer CPU Verification
Austin, TX · On-site
$171K - $296K/yr
Analyze coverage reports and assist in closing coverage gaps. * Automate regression and ... Exposure to RISC-V architecture. * Knowledge of interconnect protocols like AXI, ACE, or CHI.
Sr Principal Verification Engineer
Austin, TX · On-site
$171K - $296K/yr
Analyze coverage reports and assist in closing coverage gaps. * Automate regression and ... Exposure to RISC-V architecture. * Knowledge of interconnect protocols like AXI, ACE, or CHI.
Sr Principal Verification Engineer
Austin, TX · On-site
$171K - $296K/yr
Analyze coverage reports and assist in closing coverage gaps. * Automate regression and ... Exposure to RISC-V architecture. * Knowledge of interconnect protocols like AXI, ACE, or CHI.
Embedded Software Engineer
$150K - $250K/yr
The ideal candidate should have a strong background working with heterogeneous multi-core RISC-V or ... These tools assist our recruitment team but do not replace human judgment. Final hiring decisions ...
Embedded Software Engineer
$150K - $250K/yr
The ideal candidate should have a strong background working with heterogeneous multi-core RISC-V or ... These tools assist our recruitment team but do not replace human judgment. Final hiring decisions ...
Embedded SoC Architect
San Jose, CA · On-site
$145.60K/yr
Guide and assist pre-silicon design/verification and post-silicon validation during the execution ... Technical knowledge of Cores running either x86, RISC-V, or ARM ISA, I/O protocols such as PCIe and ...
Embedded SoC Architect
San Jose, CA · On-site
$145.60K/yr
Guide and assist pre-silicon design/verification and post-silicon validation during the execution ... Technical knowledge of Cores running either x86, RISC-V, or ARM ISA, I/O protocols such as PCIe and ...
Distinguished Embedded Software Engineer
$100K - $275K/yr
... * Assist customers to shape their needs and develop requirements for programs that solve their ... Familiarity with RISC-V architecture is preferred as is Python experience. Applicants selected for ...
Distinguished Embedded Software Engineer
$100K - $275K/yr
... * Assist customers to shape their needs and develop requirements for programs that solve their ... Familiarity with RISC-V architecture is preferred as is Python experience. Applicants selected for ...
Senior Principal IP Design Engineer
Santa Clara, CA · On-site
$188K - $325K/yr
Perform Functional verification support and assist in the design verification strategy * Assist ... Experience with designing RISC-V, ARM, and/or MIPS CPU * Experience with Hardware multi-threading ...
Senior Principal IP Design Engineer
Santa Clara, CA · On-site
$188K - $325K/yr
Perform Functional verification support and assist in the design verification strategy * Assist ... Experience with designing RISC-V, ARM, and/or MIPS CPU * Experience with Hardware multi-threading ...
Assistant Risc V information
See salary details
$29K - $32.7K
1% of jobs
$32.7K - $36.4K
4% of jobs
$36.4K - $40K
7% of jobs
$42.5K is the 25th percentile. Wages below this are outliers.
$40K - $43.7K
18% of jobs
The median wage is $46.4K / yr.
$43.7K - $47.4K
27% of jobs
$49.7K is the 75th percentile. Wages above this are outliers.
$47.4K - $51.1K
28% of jobs
$51.1K - $54.8K
7% of jobs
$54.8K - $58.5K
3% of jobs
$58.5K - $62.1K
2% of jobs
$62.1K - $65.8K
1% of jobs
$65.8K - $69.5K
1% of jobs
$29K
$48.4K
$69.5K
How much do assistant risc v jobs pay per year?
What is the difference between Assistant Risc V vs Embedded Systems Technician?
| Aspect | Assistant Risc V | Embedded Systems Technician |
|---|---|---|
| Required Credentials | Associate degree or technical certification in electronics or computer engineering | Associate degree or higher in electronics, computer engineering, or related field |
| Work Environment | Design labs, manufacturing facilities, testing environments | Industrial, manufacturing, or technology companies working on embedded systems |
| Industry Usage | Semiconductor, hardware development, embedded system design | Embedded device development, hardware troubleshooting, firmware testing |
The Assistant Risc V and Embedded Systems Technician roles share similar credentials and work environments, often overlapping in hardware and embedded system industries. While the Assistant Risc V focuses specifically on RISC-V architecture support, the Embedded Systems Technician has a broader scope across various embedded platforms. Both roles are essential in hardware development and testing, making them closely related in the tech industry.

Other
Posted 24 days ago
Job description
The IP Product Team is where deep tech meets big-picture strategy. We're the bridge between engineering brilliance and real-world impact - defining how our core IP comes to life and gets delivered to customers.
We're looking for an Intern who loves technology and wants to learn how world-class intellectual property (IP) gets transformed into world-changing products. You'll collaborate with engineers, product managers, and cross-functional teams to help shape the future of Tenstorrent's RISC-V CPU and AI IP portfolio.
This role is remote, based out of the U.S. or Canada.
Who You Are
- Currently enrolled in an Engineering, Computer Science, Business, or related undergraduate program.
- Have exposure to engineering concepts or environments - you can follow (and enjoy!) a technical conversation, even if you're not an engineer yourself.
- Have experience or a strong interest in program management, operations management, especially where technology and strategy intersect.
- A clear and confident communicator who loves translating technical detail into actionable insight.
- Highly organized, curious, and ready to take initiative in a fast-moving environment.
- Excited by semiconductors, RISC-V, AI, and the process of turning cutting-edge ideas into products that scale.
- Skilled in applying AI technology to automate, generate, analyze data.
What We Need
- Support in defining and maintaining product documentation, roadmaps, planning and release materials for Tenstorrent IP.
- Coordinate with engineering and product management teams to ensure alignment on milestones and deliverables.
- Assist in gathering and analyzing data to support product decisions and reporting using AI tools.
- Help manage internal tools and processes for IP lifecycle management and customer documentation.
- Participate in cross-functional meetings to capture action items and help drive follow-up execution
What You Will Learn
- How semiconductor IP is developed, tracked, and released at scale.
- The art and science of program management and operations in the world of RISC-V CPUs, AI and hardware innovation.
- Best practices and applying AI in documentation, communication, and product lifecycle management.
- Deep insights into RISC-V architecture, AI accelerators, and the technology shaping the future of compute.