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Design Engineer Pcie Jobs (NOW HIRING)

Cornelis Networks

PCIe ASIC Design Engineer

Austin, TX · On-site +1

Cornelis Networks is hiringa Senior ASIC Design Engineer to lead the design and integration of PCIe controllers into our next-generation SoCs. The ideal candidate will have deep expertise in PCI ...

Cornelis Networks

PCIe ASIC Design Engineer

Austin, TX · On-site

Cornelis Networks is hiring a Senior ASIC Design Engineer to lead the design and integration of PCIe controllers into our next-generation SoCs. The ideal candidate will have deep expertise in PCI ...

Google

TPU PCIe RTL Design Engineer

Sunnyvale, CA · On-site

As a PCIe Design Engineer, you will architect and implement SoC-level RTL for our next-generation data center accelerators. Beyond designing high-performance PCIe subsystems, you will build the ...

Innogrit

Design Engineer

San Jose, CA · On-site

Drive OVM/UVM design verification and support FPGA engineers for early prototyping. * Execute RTL ... Innogrit is transforming data storage with its advanced PCIe Gen 3 and Gen 4 SSD (Solid State Drive ...

Airspan

FPGA DESIGN ENGINEER

Warren, NJ · On-site

$127K - $176K/yr

Airspan Careers FPGA DESIGN ENGINEER Location: Warren, New Jersey or Plano, TX, Remote possible if ... Implement high-speed interfaces such as PCIe, Ethernet, and JESD204B . * Document design ...

IBA Infotech Inc.

RTL Design Engineer

Santa Clara, CA · Hybrid

Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We ... Python #TCL #AMBA #PCIe #LowPowerDesign to contribute across design, coding, debugging, and ...

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All JobsDesign Engineer Pcie Jobs

Design Engineer Pcie information

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$40.5K

$88.2K

$158.5K

How much do design engineer pcie jobs pay per year?

As of Aug 2, 2026, the average yearly pay for design engineer pcie in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.

What are some typical challenges a Design Engineer PCIe faces when integrating PCIe interfaces into new hardware products?

As a Design Engineer PCIe, you will often encounter challenges related to ensuring signal integrity and compatibility when integrating PCIe interfaces into hardware designs. This can involve addressing issues like high-speed signal routing, managing power consumption, and ensuring compliance with PCIe standards. Collaboration with firmware, hardware, and verification teams is common to resolve interoperability issues and optimize performance. Staying updated on the latest PCIe specifications and debugging complex system-level problems are also key aspects of the role.

What are the key skills and qualifications needed to thrive as a Design Engineer (PCIe), and why are they important?

To excel as a Design Engineer specializing in PCIe, you need a solid background in electrical or computer engineering, with expertise in high-speed digital design and thorough knowledge of PCI Express protocols. Proficiency with hardware design tools such as Cadence or Synopsys, simulation tools, and familiarity with industry standards like PCIe specifications are typically required. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help set top engineers apart. These competencies ensure robust, reliable hardware designs that meet performance standards and integrate seamlessly into complex systems.

What are Design Engineer PCIe jobs?

Design Engineer PCIe jobs involve designing, developing, and testing hardware and systems that utilize PCI Express (PCIe) technology for high-speed data transfer. These engineers work on creating circuit boards, verifying PCIe interfaces, and ensuring compliance with industry standards. Their role often includes collaborating with software and hardware teams to optimize system integration and performance. Design Engineer PCIe professionals are crucial in industries like computing, networking, and storage solutions, where reliable and fast data communication is essential.

What is the difference between Design Engineer Pcie vs Design Engineer Usb?

AspectDesign Engineer PcieDesign Engineer Usb
Required SkillsPCIe protocol, hardware design, FPGA/ASIC developmentUSB standards, hardware design, FPGA/ASIC development
Work EnvironmentSemiconductor companies, hardware development labsConsumer electronics, peripheral device companies
CertificationsRelevant hardware design certifications, industry experienceSimilar certifications, focus on interface standards

Both Design Engineer Pcie and Design Engineer Usb roles involve hardware interface design, requiring similar skills and certifications. The main difference lies in the specific protocols and standards they work with: PCIe for high-speed data transfer in computers and servers, and USB for peripheral connectivity. Their work environments and industry applications also differ, with PCIe roles often in enterprise hardware and USB roles in consumer electronics.

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Design Engineer Pcie jobs near you
Infographic showing various Design Engineer Pcie job openings in the United States as of July 2026, with employment types broken down into 88% Full Time, 9% Part Time, and 3% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $88,150 per year, or $42.4 per hour.

Principal RTL Design Engineer - PCIe / CXL / High-Speed SoC

Cybercoders

Santa Clara, CA • On-site

$300K - $350K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

This job post has expired today. Applications are no longer accepted.

Job description

Principal RTL Design Engineer - PCIe / CXL / High-Speed SoC

Job Title: Principal RTL Design Engineer - PCIe / CXL / High-Speed SoC
Location: Santa Clara, CA
Compensation: $200K - $250K base DOE plus bonus and RSUs ($300K - $350K+ total comp.)
Requirements: RTL Design, Verilog / SystemVerilog, PCIe / CXL / Ethernet / UALink, High-Speed SoC Design
Position Overview
As a Sr. Staff or Principal RTL Design Engineer, you will join the Connectivity Business Unit within the Data Center Group (DCG), contributing to the development of advanced silicon solutions for next-generation data center infrastructure. In this role, you will be instrumental in driving the design and delivery of high-performance ASICs that power industry-leading products for hyperscale and enterprise customers. This position offers the opportunity to work alongside world-class engineers, influence key design methodologies, and contribute to cutting-edge technologies in an environment that values innovation, collaboration, and execution excellence.
Key Responsibilities

  • Own and implement RTL design blocks, demonstrating strong RTL coding expertise.
  • Collaborate with the architecture team to understand and define feature enhancements.
  • Translate specifications into efficient RTL implementations.
  • Ensure all design quality standards and criteria are consistently met.
  • Partner with physical design teams to review timing reports, perform STA, write SDC constraints, analyze power, and provide guidance on floorplanning and timing closure.
  • Work closely with the verification team on pre-silicon activities, including test plan reviews, coverage analysis, simulations (block and full-chip), performance evaluation, and debugging; strong debug skills are essential.
  • Define subsystem microarchitecture and register specifications for complex SoCs, and contribute to specification development.
  • Lead and participate in detailed reviews of performance, architecture, and design requirements with cross-functional teams, IP vendors, and customers.
  • Contribute to the development and evaluation of design and verification methodologies, and help enhance existing processes.
  • Collaborate with post-silicon and software and firmware teams to support silicon bring-up and performance optimization.

Qualifications

  • Bachelor's degree in Electrical Engineering or a related field with 15+ years of relevant experience, or a Master's/PhD with 12+ years of experience.
  • Strong proficiency in Verilog/SystemVerilog RTL development, including SystemVerilog assertions.
  • Experience working on complex subsystems, IPs, or switch SoCs involving PCIe, CXL, Ethernet, or UALink.
  • Deep knowledge of PCIe, CXL, Ethernet, or UALink protocols.
  • Expertise in microarchitecture development and translating requirements into robust designs.
  • Proven ability to collaborate effectively with third-party IP vendors and customers.
  • Extensive experience in RTL design, synthesis, constraint development, static timing analysis, debugging, block-level functional verification, logical equivalence checking, and CDC/RDC.
  • Solid experience with implementation and timing closure for high-speed designs.
  • Hands-on experience across the full chip development lifecycle, with strong proficiency in front-end and mid-end design tools and methodologies.

Benefits

  • Comprehensive medical, dental, and vision plans
  • Life insurance and disability plan options
  • 401(k)
  • RSUs
  • ESPP
  • Paid company-selected holidays & floating holidays
  • PTO - generous time off programs
  • Career growth opportunities
     
- For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa. CyberCoders will consider for Employment in the City of Los Angeles qualified Applicants with Criminal Histories in a manner consistent with the requirements of the Los Angeles Fair Chance Initiative for Hiring (Ban the Box) Ordinance.This job was first posted by CyberCoders on 06/25/2026 and applications will be accepted on an ongoing basis until the position is filled or closed.Everforth CyberCoders is proud to be an Equal Opportunity Employer
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. Our hiring process includes AI screening for keywords and minimum qualifications, and a virtual recruiter as part of the application process. A human recruiter reviews all results. Click here for details on our virtual recruiter .  Everforth CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. Everforth CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. Individuals needing special assistance or an accommodation while seeking employment can contact a member of our Human Resources team at Benefits@CyberCoders.com to make arrangements.

Salary

$200000 - $250000 USD per year
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About CyberCoders

Sourced by ZipRecruiter

CyberCoders is a cutting-edge recruiting firm headquartered in Irvine, CA, US. The company operates within the technology industry, specializing in connecting talented professionals with suitable positions across a variety of sectors. Offering a broad spectrum of services, CyberCoders uses innovative, data-driven strategies and a proprietary matching technology to pair candidates with suitable job openings. Since its inception in 1999, CyberCoders has distinguished itself as an industry trailblazer. The company's mission is to deliver effective talent solutions, thus enabling both businesses and workers to achieve their goals.

Industry

Technology, communication and media

Company size

51 - 200 Employees

Headquarters location

Irvine, CA, US

Year founded

1999

Social media

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