ZipRecruiter

Log In

1

Design Engineer Pcie Jobs in Novato, CA (NOW HIRING)

TenX Semi

Chip Design Engineer

San Francisco, CA · On-site

$140 - $210/hr

Build protocol implementations (PCIe, DDR, AXI, etc.) for customer requirements. What You Bring ... Familiarity with AI/ML concepts and interest in AI-assisted design. * MS in Electrical Engineering ...

New

United Airlines

Hardware Design Engineer

San Francisco, CA · On-site

$65K - $169K/yr

Hands-on experience with networking and communication protocols (e.g., Ethernet, PCIe, MIPI, GMSL ... and design to engineering, all fueled by its market leading capabilities in AI, generative AI ...

Apple

SerDes Circuit Design Engineer

San Francisco, CA · On-site

$238K/yr

In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to ... g., PCIe, USB, DP, MPHY) Skills in scripting and automation to enhance efficiency are highly ...

Flux

Head of Hardware Design

San Francisco, CA · On-site

$245K - $270K/yr

To do this, we're building the world's first AI hardware engineer. Founded in 2019, our platform ... DDRx, PCIe/SerDes, USB‑C/USB4, MIPI, Ethernet (1G-25G+); timing, skew, and equalization ...

Apple

Design Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

We have an opportunity for an outstandingly hardworking design verification engineer! As a member ... PCIe or USB, parallel protocol such as DDR is a plus but not required Knowledge of formal ...

Apple

Design Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

We have an opportunity for an outstandingly hardworking design verification engineer. As a member ... such as PCIe or USB, parallel protocol such as DDR Basic knowledge of formal verification ...

Apple

Design Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

We have an opportunity for an outstandingly hardworking design verification engineer. As a member ... such as PCIe or USB, parallel protocol such as DDR Basic knowledge of formal verification ...

Virtusa Corporation

Software Engineer

San Francisco, CA · On-site

Application or Product Engineering background with minimum 5 to 10 years of experience is required ... PCIe IP [Gen1 to Gen6/7] plus PHY in subsystem or SOC level . Skills Requirements Digital design ...

OpenAI

ASIC Package SI/PI Engineer

San Francisco, CA · On-site

$266K - $445K/yr

Develop and optimize high-speed electrical channels for 200G/400G SerDes, PCIe, HBM, DDR, and ... Drive die/package co-design, including bump/BGA assignment, stack-up optimization, power/ground ...

Slope

ASIC Package SI/PI Engineer

San Francisco, CA · On-site

$180 - $240/hr

Develop and optimize high-speed electrical channels for 200G/400G SerDes, PCIe, HBM, DDR, and ... Drive die/package co-design, including bump/BGA assignment, stack-up optimization, power/ground ...

next page

Showing results 1-20

All JobsDesign Engineer Pcie JobsDesign Engineer Pcie Jobs in Novato, CA

Design Engineer Pcie information

See Novato, CA salary details

$47.5K

$103.5K

$186.1K

How much do design engineer pcie jobs pay per year?

As of Sep 3, 2026, the average yearly pay for design engineer pcie in Novato, CA is $103,493.00, according to ZipRecruiter salary data. Most workers in this role earn between $79,800.00 and $115,600.00 per year, depending on experience, location, and employer.

What is a design engineer PCIe?

Design Engineer PCIe jobs involve designing, developing, and testing hardware and systems that utilize PCI Express (PCIe) technology for high-speed data transfer. These engineers work on creating circuit boards, verifying PCIe interfaces, and ensuring compliance with industry standards. Their role often includes collaborating with software and hardware teams to optimize system integration and performance. Design Engineer PCIe professionals are crucial in industries like computing, networking, and storage solutions, where reliable and fast data communication is essential.

What are some typical challenges a design engineer PCIe faces when integrating PCIe interfaces into new hardware products?

As a Design Engineer PCIe, you will often encounter challenges related to ensuring signal integrity and compatibility when integrating PCIe interfaces into hardware designs. This can involve addressing issues like high-speed signal routing, managing power consumption, and ensuring compliance with PCIe standards. Collaboration with firmware, hardware, and verification teams is common to resolve interoperability issues and optimize performance. Staying updated on the latest PCIe specifications and debugging complex system-level problems are also key aspects of the role.

What are the key skills and qualifications needed to thrive as a design engineer PCIe, and why are they important?

To excel as a Design Engineer specializing in PCIe, you need a solid background in electrical or computer engineering, with expertise in high-speed digital design and thorough knowledge of PCI Express protocols. Proficiency with hardware design tools such as Cadence or Synopsys, simulation tools, and familiarity with industry standards like PCIe specifications are typically required. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help set top engineers apart. These competencies ensure robust, reliable hardware designs that meet performance standards and integrate seamlessly into complex systems.

What is the difference between Design Engineer Pcie vs Design Engineer Usb?

AspectDesign Engineer PcieDesign Engineer Usb
Required SkillsPCIe protocol, hardware design, FPGA/ASIC developmentUSB standards, hardware design, FPGA/ASIC development
Work EnvironmentSemiconductor companies, hardware development labsConsumer electronics, peripheral device companies
CertificationsRelevant hardware design certifications, industry experienceSimilar certifications, focus on interface standards

Both Design Engineer Pcie and Design Engineer Usb roles involve hardware interface design, requiring similar skills and certifications. The main difference lies in the specific protocols and standards they work with: PCIe for high-speed data transfer in computers and servers, and USB for peripheral connectivity. Their work environments and industry applications also differ, with PCIe roles often in enterprise hardware and USB roles in consumer electronics.

What cities near Novato, CA are hiring for Design Engineer Pcie jobs?

Cities near Novato, CA with the most Design Engineer Pcie job openings:

Design Engineer Pcie jobs near you
Infographic showing various Design Engineer Pcie job openings in Novato, CA as of August 2026, with employment types broken down into 1% Internship, 86% Full Time, 8% Part Time, and 5% Contract. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution, with an average salary of $103,493 per year, or $49.8 per hour.

Chip Design Engineer

TenX Semi

San Francisco, CA • On-site

$140 - $210/hr

Other

Posted 2 days ago

New

Job description

San Francisco Bay Area, CA · Hybrid · Full-time

We are looking for a Chip Design Engineer who works on strategic customer engagements, developing custom IP and optimizing designs for power, performance, and area. You will collaborate closely with our AI systems, providing the domain expertise that ensures AI-generated designs meet real-world requirements.

In this role, you will combine hands-on RTL design with exposure to cutting-edge AI technology. You will help shape how AI and human expertise work together in chip design. Your designs will go into production at the world's leading technology companies.

What You Will Do
  • Design RTL for Customer Projects: Implement RTL for strategic customer engagements. You will write clean, synthesizable, timing-aware Verilog/SystemVerilog.
  • Optimize for PPA: Analyze and optimize designs for power, performance, and area. Your optimizations will contribute to royalty-generating designs.
  • Support Synthesis and Timing: Work through synthesis and timing closure. You understand what makes RTL synthesizable and how to fix timing violations.
  • Improve AI-Generated Designs: Review and enhance AI-generated RTL for production quality. Your feedback will improve model accuracy.
  • Develop Reference Implementations: Create high-quality reference designs that become training data for our AI models.
  • Implement Protocol Blocks: Build protocol implementations (PCIe, DDR, AXI, etc.) for customer requirements.
What You Bring (Required)
  • RTL Design Experience: You have 5+ years of experience designing production RTL. You write clean, readable, synthesizable Verilog/SystemVerilog.
  • Micro-Architecture Understanding: You have solid understanding of pipeline design, FSMs, arbitration, and data flow. You can translate architecture specs into RTL.
  • Synthesis Awareness: You have experience with synthesis tools (Design Compiler, Genus). You understand what makes RTL timing-friendly.
  • Debug Skills: You can read waveforms, trace signal paths, and debug complex logic issues. You have experience with Verdi, SimVision, or similar tools.
  • PPA Intuition: You understand power-performance-area tradeoffs. You can make informed design decisions based on PPA goals.
  • Collaborative Mindset: You work well with verification engineers, architects, and AI engineers. You communicate clearly and give/receive feedback well.
Bonus Points (Preferred)
  • Experience at leading semiconductor companies (Intel, AMD, NVIDIA, Qualcomm, Broadcom, Marvell, MediaTek).
  • Protocol implementation experience (PCIe, DDR, AXI, AHB, APB, CHI).
  • Physical design awareness (floor planning, clock tree, routing congestion).
  • Background in accelerator, SoC, or high-performance computing design.
  • Familiarity with AI/ML concepts and interest in AI-assisted design.
  • MS in Electrical Engineering or Computer Science.
Why Join Us

You will be at the forefront of AI-assisted chip design—a fundamental transformation in how chips are built. Your designs will go into production at top tech companies. You'll learn cutting-edge AI while applying your chip design expertise, building skills that will define the future of the industry.

#J-18808-Ljbffr

Apply