Analog Design Engineer
$206K/yr
... PCIe, SPI, I2C, UART, GPIO, DDR, Ethernet, ARINC, 1553, etc.) • High-speed interface design and ... Engineering, Operations, and Quality teams for defect resolution • Drive design and process ...
Analog Design Engineer
$206K/yr
... PCIe, SPI, I2C, UART, GPIO, DDR, Ethernet, ARINC, 1553, etc.) • High-speed interface design and ... Engineering, Operations, and Quality teams for defect resolution • Drive design and process ...
Senior FPGA Design Engineer
Yorktown Heights, NY · Remote
$125K - $173K/yr
Role: Senior FPGA Design Engineer Location: Remote Duration: 12+ Months Contract Job Summary ... Job Duty 1 - Design (and implement) PCIe-to-Interlaken section of the Host FPGA Data Path.
Quick apply
Senior FPGA Design Engineer
Yorktown Heights, NY · Remote
$125K - $173K/yr
Role: Senior FPGA Design Engineer Location: Remote Duration: 12+ Months Contract Job Summary ... Job Duty 1 - Design (and implement) PCIe-to-Interlaken section of the Host FPGA Data Path.
CPU, GPU / ML accelerator, networking, memory subsystem, PCIe / high-speed IO, SoC interconnect ... Design Verification Engineer * 3, 10 years of experience in design verification * Strong ...
New
CPU, GPU / ML accelerator, networking, memory subsystem, PCIe / high-speed IO, SoC interconnect ... Design Verification Engineer * 3, 10 years of experience in design verification * Strong ...
New
Staff Design Verification Engineer - PCIE/CXL Subsystem COE
Santa Clara, CA · On-site
$159K - $195K/yr
... spanning PCIe/CXL, Ethernet, DDR/Memory, Security/Boot, Low-Speed IO, and other critical ... As part of the COE, you will design, verify, and deliver IP subsystem building blocks powering ...
Staff Design Verification Engineer - PCIE/CXL Subsystem COE
Santa Clara, CA · On-site
$159K - $195K/yr
... spanning PCIe/CXL, Ethernet, DDR/Memory, Security/Boot, Low-Speed IO, and other critical ... As part of the COE, you will design, verify, and deliver IP subsystem building blocks powering ...
CPU, GPU / ML accelerator, networking, memory subsystem, PCIe / high-speed IO, SoC interconnect ... Design Verification Engineer * 3, 10 years of experience in design verification * Strong ...
New
CPU, GPU / ML accelerator, networking, memory subsystem, PCIe / high-speed IO, SoC interconnect ... Design Verification Engineer * 3, 10 years of experience in design verification * Strong ...
New
RTL Design Engineer Building AI chips that are hard-coded for individual model architectures. RTL ... Experience with PCIe, Ethernet, or HBM technologies * Familiarity with transformer models and ...
Quick apply
RTL Design Engineer Building AI chips that are hard-coded for individual model architectures. RTL ... Experience with PCIe, Ethernet, or HBM technologies * Familiarity with transformer models and ...
Principle Hardware Design Engineer - Systems Engineering
Santa Clara, CA · On-site
$150K - $225K/yr
Principle Hardware Design Engineer - Systems Engineering Location: Santa Clara, CA (100% On-site ... Execute comprehensive engineering designs utilizing high-speed differential pairs, PCIe Gen4/Gen5 ...
Principle Hardware Design Engineer - Systems Engineering
Santa Clara, CA · On-site
$150K - $225K/yr
Principle Hardware Design Engineer - Systems Engineering Location: Santa Clara, CA (100% On-site ... Execute comprehensive engineering designs utilizing high-speed differential pairs, PCIe Gen4/Gen5 ...
Principle Hardware Design Engineer - Systems Engineering
Santa Clara, CA · On-site
$150K - $225K/yr
Principle Hardware Design Engineer - Systems Engineering Location: Santa Clara, CA (100% On-site ... Execute comprehensive engineering designs utilizing high-speed differential pairs, PCIe Gen4/Gen5 ...
Principle Hardware Design Engineer - Systems Engineering
Santa Clara, CA · On-site
$150K - $225K/yr
Principle Hardware Design Engineer - Systems Engineering Location: Santa Clara, CA (100% On-site ... Execute comprehensive engineering designs utilizing high-speed differential pairs, PCIe Gen4/Gen5 ...
PCIe Software Engineer
Austin, TX · On-site
PCIe software engineers write the code that manages high speed communication between hardware components in our switches. We work with hardware, diagnostics, and software engineers to maximize ...
PCIe Software Engineer
Austin, TX · On-site
PCIe software engineers write the code that manages high speed communication between hardware components in our switches. We work with hardware, diagnostics, and software engineers to maximize ...
MICROARCHITECT AND RTL DESIGN ENGINEER SANTA CLARA, CA About the role: We are seeking a seasoned ... Familiarity with RAS designs, QoS in fabrics, PCIe/IO is a plus * Experience with modern ...
MICROARCHITECT AND RTL DESIGN ENGINEER SANTA CLARA, CA About the role: We are seeking a seasoned ... Familiarity with RAS designs, QoS in fabrics, PCIe/IO is a plus * Experience with modern ...
Staff Design Verification Engineer - PCIE/CXL Subsystem COE
Santa Clara, CA · On-site
$160K - $196K/yr
... spanning PCIe/CXL, Ethernet, DDR/Memory, Security/Boot, Low-Speed IO, and other critical ... As part of the COE, you will design, verify, and deliver IP subsystem building blocks powering ...
New
Staff Design Verification Engineer - PCIE/CXL Subsystem COE
Santa Clara, CA · On-site
$160K - $196K/yr
... spanning PCIe/CXL, Ethernet, DDR/Memory, Security/Boot, Low-Speed IO, and other critical ... As part of the COE, you will design, verify, and deliver IP subsystem building blocks powering ...
New
PCIe Software Engineer
Nashua, NH · On-site
PCIe software engineers write the code that manages high speed communication between hardware components in our switches. We work with hardware, diagnostics, and software engineers to maximize ...
New
PCIe Software Engineer
Nashua, NH · On-site
PCIe software engineers write the code that manages high speed communication between hardware components in our switches. We work with hardware, diagnostics, and software engineers to maximize ...
New
PCIe software engineers write the code that manages high speed communication between hardware components in our switches. We work with hardware, diagnostics, and software engineers to maximize ...
New
PCIe software engineers write the code that manages high speed communication between hardware components in our switches. We work with hardware, diagnostics, and software engineers to maximize ...
New
FPGA Design Engineer
$135K - $225K/yr
The best engineers, corporate professionals, and technicians make their teammates better. Knowing ... PCIe (Gen 1/2/3/4/5), 1G/10G/25G Ethernet MAC/PHY layers (SGMII, RGMII, UXSGMII) * Design and ...
New
Quick apply
FPGA Design Engineer
$135K - $225K/yr
The best engineers, corporate professionals, and technicians make their teammates better. Knowing ... PCIe (Gen 1/2/3/4/5), 1G/10G/25G Ethernet MAC/PHY layers (SGMII, RGMII, UXSGMII) * Design and ...
New
Staff Design Verification Engineer - PCIE/CXL Subsystem COE
Santa Clara, CA · On-site
$159K - $195K/yr
... spanning PCIe/CXL, Ethernet, DDR/Memory, Security/Boot, Low-Speed IO, and other critical ... As part of the COE, you will design, verify, and deliver IP subsystem building blocks powering ...
Staff Design Verification Engineer - PCIE/CXL Subsystem COE
Santa Clara, CA · On-site
$159K - $195K/yr
... spanning PCIe/CXL, Ethernet, DDR/Memory, Security/Boot, Low-Speed IO, and other critical ... As part of the COE, you will design, verify, and deliver IP subsystem building blocks powering ...
FPGA Design Engineer
Long Beach, CA · On-site
$129K - $178K/yr
The best engineers, corporate professionals, and technicians make their teammates better. Knowing ... PCIe (Gen 1/2/3/4/5), 1G/10G/25G Ethernet MAC/PHY layers (SGMII, RGMII, UXSGMII) * Design and ...
New
FPGA Design Engineer
Long Beach, CA · On-site
$129K - $178K/yr
The best engineers, corporate professionals, and technicians make their teammates better. Knowing ... PCIe (Gen 1/2/3/4/5), 1G/10G/25G Ethernet MAC/PHY layers (SGMII, RGMII, UXSGMII) * Design and ...
New
FPGA Design Engineer
Long Beach, CA · On-site
$129K - $178K/yr
The best engineers, corporate professionals, and technicians make their teammates better. Knowing ... PCIe (Gen 1/2/3/4/5), 1G/10G/25G Ethernet MAC/PHY layers (SGMII, RGMII, UXSGMII) * Design and ...
New
FPGA Design Engineer
Long Beach, CA · On-site
$129K - $178K/yr
The best engineers, corporate professionals, and technicians make their teammates better. Knowing ... PCIe (Gen 1/2/3/4/5), 1G/10G/25G Ethernet MAC/PHY layers (SGMII, RGMII, UXSGMII) * Design and ...
New
Principal Digital Design Engineer
$185K - $230K/yr
PCIe, CXL, Ethernet, DDR, or similar * Production experience with advanced CMOS nodes (7nm ... digital design flows Preferred Qualifications * Master's degree in Electrical Engineering or ...
Principal Digital Design Engineer
$185K - $230K/yr
PCIe, CXL, Ethernet, DDR, or similar * Production experience with advanced CMOS nodes (7nm ... digital design flows Preferred Qualifications * Master's degree in Electrical Engineering or ...
Digital Design Engineer
Tucson, AZ · On-site
$128K/yr
... PCIe, Ethernet, I2C, SPI, and UART. The candidate will be working in a collaborative team ... of engineering digital circuit design experience to include at least 2 of the following:
Digital Design Engineer
Tucson, AZ · On-site
$128K/yr
... PCIe, Ethernet, I2C, SPI, and UART. The candidate will be working in a collaborative team ... of engineering digital circuit design experience to include at least 2 of the following:
Silicon Design Engineer
San Jose, CA · On-site
Xilinx, Inc., a subsidiary of AMD, Inc., is hiring Silicon Design Engineer to Research, design ... Designing and implementing PCIe/CXL protocol related logic, including LTSSM, TLP/DLLP handling ...
Silicon Design Engineer
San Jose, CA · On-site
Xilinx, Inc., a subsidiary of AMD, Inc., is hiring Silicon Design Engineer to Research, design ... Designing and implementing PCIe/CXL protocol related logic, including LTSSM, TLP/DLLP handling ...
Design Engineer Pcie information
See salary details
$40.5K - $51.2K
2% of jobs
$51.2K - $62K
11% of jobs
$67.7K is the 25th percentile. Wages below this are outliers.
$62K - $72.7K
23% of jobs
The median wage is $79.6K / yr.
$72.7K - $83.4K
22% of jobs
$83.4K - $94.1K
17% of jobs
$94.4K is the 75th percentile. Wages above this are outliers.
$94.1K - $104.9K
9% of jobs
$104.9K - $115.6K
6% of jobs
$115.6K - $126.3K
3% of jobs
$126.3K - $137K
3% of jobs
$137K - $147.8K
2% of jobs
$147.8K - $158.5K
1% of jobs
$40.5K
$88.2K
$158.5K
How much do design engineer pcie jobs pay per year?
As of Jul 12, 2026, the average yearly pay for design engineer pcie in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.
What are some typical challenges a Design Engineer PCIe faces when integrating PCIe interfaces into new hardware products?
As a Design Engineer PCIe, you will often encounter challenges related to ensuring signal integrity and compatibility when integrating PCIe interfaces into hardware designs. This can involve addressing issues like high-speed signal routing, managing power consumption, and ensuring compliance with PCIe standards. Collaboration with firmware, hardware, and verification teams is common to resolve interoperability issues and optimize performance. Staying updated on the latest PCIe specifications and debugging complex system-level problems are also key aspects of the role.
What are the key skills and qualifications needed to thrive as a Design Engineer (PCIe), and why are they important?
To excel as a Design Engineer specializing in PCIe, you need a solid background in electrical or computer engineering, with expertise in high-speed digital design and thorough knowledge of PCI Express protocols. Proficiency with hardware design tools such as Cadence or Synopsys, simulation tools, and familiarity with industry standards like PCIe specifications are typically required. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help set top engineers apart. These competencies ensure robust, reliable hardware designs that meet performance standards and integrate seamlessly into complex systems.
What are Design Engineer PCIe jobs?
Design Engineer PCIe jobs involve designing, developing, and testing hardware and systems that utilize PCI Express (PCIe) technology for high-speed data transfer. These engineers work on creating circuit boards, verifying PCIe interfaces, and ensuring compliance with industry standards. Their role often includes collaborating with software and hardware teams to optimize system integration and performance. Design Engineer PCIe professionals are crucial in industries like computing, networking, and storage solutions, where reliable and fast data communication is essential.
What is the difference between Design Engineer Pcie vs Design Engineer Usb?
| Aspect | Design Engineer Pcie | Design Engineer Usb |
|---|---|---|
| Required Skills | PCIe protocol, hardware design, FPGA/ASIC development | USB standards, hardware design, FPGA/ASIC development |
| Work Environment | Semiconductor companies, hardware development labs | Consumer electronics, peripheral device companies |
| Certifications | Relevant hardware design certifications, industry experience | Similar certifications, focus on interface standards |
Both Design Engineer Pcie and Design Engineer Usb roles involve hardware interface design, requiring similar skills and certifications. The main difference lies in the specific protocols and standards they work with: PCIe for high-speed data transfer in computers and servers, and USB for peripheral connectivity. Their work environments and industry applications also differ, with PCIe roles often in enterprise hardware and USB roles in consumer electronics.
More about Design Engineer Pcie jobs
What cities are hiring for Design Engineer Pcie jobs? Cities with the most Design Engineer Pcie job openings:
What states have the most Design Engineer Pcie jobs? States with the most job openings for Design Engineer Pcie jobs include:
What job categories do people searching Design Engineer Pcie jobs look for? The top searched job categories for Design Engineer Pcie jobs are:
Job description
• Design of complex analog circuit card assemblies
• Design, analysis, and verification of analog circuits for FPGA and microcontroller interfaces (PCIe, SPI, I2C, UART, GPIO, DDR, Ethernet, ARINC, 1553, etc.)
• High-speed interface design and signal integrity verification
• Circuit design activities including component selection, schematic capture, PCB support, simulation, and testing
• Support testing and troubleshooting of systems and sub-assemblies
• Work closely with PCB layout and packaging teams
• Prepare and review technical documentation (test procedures, specifications, ECOs, reports, etc.)
• Collaborate with Engineering, Operations, and Quality teams for defect resolution
• Drive design and process improvements to enhance performance and efficiency
• Provide training and support to technicians and manufacturing teams
• Lead or mentor junior engineers as required
• Interface with customers and suppliers
• Present designs in internal and customer review meetings
• Support legacy design updates and reverse engineering
Must Have Skills:
• EMI and lightning protection experience
• Experience with Siemens (Mentor) DX Designer
• Experience with HyperLynx
About SAPSOL Technologies Inc. : Systems and Process Solutions for your Enterprise
Sourced by ZipRecruiter
Industry
It services
Company size
11 - 50 Employees
Headquarters location
Santa Clara, CA, US
Year founded
2006