ZipRecruiter

Log In

1

Design Engineer Pcie Jobs (NOW HIRING)

Innogrit

Design Engineer

San Jose, CA · On-site

Drive OVM/UVM design verification and support FPGA engineers for early prototyping. * Execute RTL ... Innogrit is transforming data storage with its advanced PCIe Gen 3 and Gen 4 SSD (Solid State Drive ...

Airspan

FPGA DESIGN ENGINEER

Warren, NJ · On-site

$127K - $176K/yr

Airspan Careers FPGA DESIGN ENGINEER Location: Warren, New Jersey or Plano, TX, Remote possible if ... Implement high-speed interfaces such as PCIe, Ethernet, and JESD204B . * Document design ...

Info Way Solutions

FPGA Design Engineer

Melbourne, FL · On-site

$114K - $157K/yr

FPGA Design Engineer Location: Melbourne, FL (Onsite) Duration: 6+ months Start Date: Immediate We ... Experience with high-speed interfaces including PCIe, Ethernet, DDR, SPI, I2C, UART, or JESD204.

New

IBA Infotech Inc.

RTL Design Engineer

Santa Clara, CA · On-site

Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We ... Python #TCL #AMBA #PCIe #LowPowerDesign to contribute across design, coding, debugging, and ...

IBA Infotech Inc.

RTL Design Engineer

Santa Clara, CA · Hybrid

Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We ... Python #TCL #AMBA #PCIe #LowPowerDesign to contribute across design, coding, debugging, and ...

TylSemi

PCIe Subsystem RTL lead

San Jose, CA · On-site

$159K - $164K/yr

Mentor and guide RTL design engineers responsible for PCIe subsystem implementation, providing architectural guidance and RTL review. * Partner with the DV team to define the PCIe UVM verification ...

Teledyne FLIR LLC

Staff Logic Design Engineer

Milpitas, CA · On-site

$141K - $189K/yr

Integrate PCIe IP cores, DMA engines, and custom protocol decoders. * Verification & Debug * Build ... design practices. Required Qualifications * BS in EE, CS or Computer Engineering required * MS in ...

Teledyne

Staff Logic Design Engineer

Milpitas, CA

$141K - $189K/yr

Integrate PCIe IP cores, DMA engines, and custom protocol decoders. * Verification & Debug * Build ... design practices. Required Qualifications * BS in EE, CS or Computer Engineering required * MS in ...

Lumilens

Design Engineer

San Jose, CA · On-site

Design Engineer/ Front-End Engineer / RTL Datapath Engineer About the role. You design and ... High-speed datapath, SerDes-adjacent, or interface design exposure (UCIe, PCIe/CXL, or similar)

New

Purple Hires Inc

Analog Design Engineer

Endicott, NY · On-site

$192K/yr

... as PCIe, SPI, I2C, UART, GPIO, DDR, Ethernet, ARINC, 1553, etc. * Design, simulation, and ... Work closely with PWB packaging and layout engineers * Generate and review engineering ...

New

Unigen

Senior Hardware Design Engineer

Newark, CA · On-site

$130K - $150K/yr

Senior Hardware Design Engineer Reports To: Sr. Director, Hardware & Systems Engineering Job ... and PCIe Gen 5/6. * Power & Signal Integrity: Define and optimize robust board-level power ...

next page

Showing results 1-20

All JobsDesign Engineer Pcie Jobs

Design Engineer Pcie information

See salary details

$40.5K

$88.2K

$158.5K

How much do design engineer pcie jobs pay per year?

As of Jul 12, 2026, the average yearly pay for design engineer pcie in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.

What are some typical challenges a Design Engineer PCIe faces when integrating PCIe interfaces into new hardware products?

As a Design Engineer PCIe, you will often encounter challenges related to ensuring signal integrity and compatibility when integrating PCIe interfaces into hardware designs. This can involve addressing issues like high-speed signal routing, managing power consumption, and ensuring compliance with PCIe standards. Collaboration with firmware, hardware, and verification teams is common to resolve interoperability issues and optimize performance. Staying updated on the latest PCIe specifications and debugging complex system-level problems are also key aspects of the role.

What are the key skills and qualifications needed to thrive as a Design Engineer (PCIe), and why are they important?

To excel as a Design Engineer specializing in PCIe, you need a solid background in electrical or computer engineering, with expertise in high-speed digital design and thorough knowledge of PCI Express protocols. Proficiency with hardware design tools such as Cadence or Synopsys, simulation tools, and familiarity with industry standards like PCIe specifications are typically required. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help set top engineers apart. These competencies ensure robust, reliable hardware designs that meet performance standards and integrate seamlessly into complex systems.

What are Design Engineer PCIe jobs?

Design Engineer PCIe jobs involve designing, developing, and testing hardware and systems that utilize PCI Express (PCIe) technology for high-speed data transfer. These engineers work on creating circuit boards, verifying PCIe interfaces, and ensuring compliance with industry standards. Their role often includes collaborating with software and hardware teams to optimize system integration and performance. Design Engineer PCIe professionals are crucial in industries like computing, networking, and storage solutions, where reliable and fast data communication is essential.

What is the difference between Design Engineer Pcie vs Design Engineer Usb?

AspectDesign Engineer PcieDesign Engineer Usb
Required SkillsPCIe protocol, hardware design, FPGA/ASIC developmentUSB standards, hardware design, FPGA/ASIC development
Work EnvironmentSemiconductor companies, hardware development labsConsumer electronics, peripheral device companies
CertificationsRelevant hardware design certifications, industry experienceSimilar certifications, focus on interface standards

Both Design Engineer Pcie and Design Engineer Usb roles involve hardware interface design, requiring similar skills and certifications. The main difference lies in the specific protocols and standards they work with: PCIe for high-speed data transfer in computers and servers, and USB for peripheral connectivity. Their work environments and industry applications also differ, with PCIe roles often in enterprise hardware and USB roles in consumer electronics.

More about Design Engineer Pcie jobs
What cities are hiring for Design Engineer Pcie jobs? Cities with the most Design Engineer Pcie job openings:
What states have the most Design Engineer Pcie jobs? States with the most job openings for Design Engineer Pcie jobs include:
What job categories do people searching Design Engineer Pcie jobs look for? The top searched job categories for Design Engineer Pcie jobs are:
Design Engineer Pcie jobs near you
Infographic showing various Design Engineer Pcie job openings in the United States as of July 2026, with employment types broken down into 89% Full Time, 8% Part Time, and 3% Contract. Highlights an 87% Physical, 3% Hybrid, and 10% Remote job distribution, with an average salary of $88,150 per year, or $42.4 per hour.
Senior Firmware Engineer - PCIe/CXL Memory Solutions

Senior Firmware Engineer - PCIe/CXL Memory Solutions

Astera Labs

San Jose, CA • On-site

$140K - $185K/yr

Full-time

Re-posted 2 days ago

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Astera Labs is seeking experienced Senior Firmware Engineer PCIe/CXL Memory Solution to lead the design and development of embedded firmware for cutting-edge PCIe/CXL memory expansion products tailored for AI and Cloud infrastructure. This role is pivotal in enabling next-generation memory devices that power high-performance computing platforms. This position will be required onsite.
Required Experience:
  • Bachelor's degree in Electrical Engineering, Computer Science, or a related technical field.
  • 5+ years of hands-on experience in embedded firmware development using C.
  • Deep expertise in low-level firmware for hardware bring-up, traffic enablement, and RAS (Reliability, Availability, Serviceability) feature implementation.
  • Proven track record working with high-speed interfaces and protocols such as PCIe, CXL, DDR, and I2C.
  • Hands on experience in CPU to Device, Device to Device flows like MMIO, DMA, PCIe P2P.

Key Responsibilities & Skills:
  • Firmware development, bring-up, and validation of PCIe/CXL/DDR interfaces at PHY and Link layers.
  • Interpret technical specifications and develop robust, low-level C code in RTOS environments.
  • Collaborate effectively with cross-functional teams and external partners to deliver weekly firmware releases and feature demonstrations.
  • Strong debugging skills and ability to triage and resolve issues in complex embedded systems.
  • Familiarity with server I/O and memory workflows, performance tuning for latency and bandwidth optimization is a plus.
  • Experience with pre-silicon validation in emulation environments is desirable.

The base salary range is 147,000 USD - 165,000 USD for Senior, 175,000 USD - 195,000 USD for Staff, 203,000 USD - 230,000 USD for Principal. Your base salary will be determined based on your relevant experience and the pay of employees in similar positions. This role may be eligible for discretionary bonus, equity, and employee benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Apply