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Design Engineer Pcie Jobs (NOW HIRING)

Innogrit

Design Engineer

San Jose, CA · On-site

Drive OVM/UVM design verification and support FPGA engineers for early prototyping. * Execute RTL ... Innogrit is transforming data storage with its advanced PCIe Gen 3 and Gen 4 SSD (Solid State Drive ...

Airspan

FPGA DESIGN ENGINEER

Warren, NJ · On-site

$127K - $176K/yr

Airspan Careers FPGA DESIGN ENGINEER Location: Warren, New Jersey or Plano, TX, Remote possible if ... Implement high-speed interfaces such as PCIe, Ethernet, and JESD204B . * Document design ...

IBA Infotech Inc.

RTL Design Engineer

Santa Clara, CA · On-site

Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We ... Python #TCL #AMBA #PCIe #LowPowerDesign to contribute across design, coding, debugging, and ...

IBA Infotech Inc.

RTL Design Engineer

Santa Clara, CA · Hybrid

Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We ... Python #TCL #AMBA #PCIe #LowPowerDesign to contribute across design, coding, debugging, and ...

Intellectt INC

FPGA Design Engineer

Plano, TX · On-site

$117K - $162K/yr

FPGA Design Engineer Location: Plano, Texas Job Summary Seeking a Senior FPGA Engineer with 7+ ... Knowledge of DDR, PCIe, I2C, UART, and Ethernet interfaces. * Experience with Python, Perl, or Tcl ...

Teledyne FLIR LLC

Staff Logic Design Engineer

Milpitas, CA · On-site

$141K - $189K/yr

Integrate PCIe IP cores, DMA engines, and custom protocol decoders. * Verification & Debug * Build ... design practices. Required Qualifications * BS in EE, CS or Computer Engineering required * MS in ...

Teledyne

Staff Logic Design Engineer

Milpitas, CA

$141K - $189K/yr

Integrate PCIe IP cores, DMA engines, and custom protocol decoders. * Verification & Debug * Build ... design practices. Required Qualifications * BS in EE, CS or Computer Engineering required * MS in ...

TylSemi

PCIe Subsystem RTL lead

San Jose, CA · On-site

$159K - $164K/yr

... design engineers responsible for PCIe subsystem implementation, providing architectural guidance and RTL review. • Partner with the DV team to define the PCIe UVM verification plan, coverage model ...

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All JobsDesign Engineer Pcie Jobs

Design Engineer Pcie information

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$40.5K

$88.2K

$158.5K

How much do design engineer pcie jobs pay per year?

As of Jun 21, 2026, the average yearly pay for design engineer pcie in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.

What are some typical challenges a Design Engineer PCIe faces when integrating PCIe interfaces into new hardware products?

As a Design Engineer PCIe, you will often encounter challenges related to ensuring signal integrity and compatibility when integrating PCIe interfaces into hardware designs. This can involve addressing issues like high-speed signal routing, managing power consumption, and ensuring compliance with PCIe standards. Collaboration with firmware, hardware, and verification teams is common to resolve interoperability issues and optimize performance. Staying updated on the latest PCIe specifications and debugging complex system-level problems are also key aspects of the role.

What are the key skills and qualifications needed to thrive as a Design Engineer (PCIe), and why are they important?

To excel as a Design Engineer specializing in PCIe, you need a solid background in electrical or computer engineering, with expertise in high-speed digital design and thorough knowledge of PCI Express protocols. Proficiency with hardware design tools such as Cadence or Synopsys, simulation tools, and familiarity with industry standards like PCIe specifications are typically required. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help set top engineers apart. These competencies ensure robust, reliable hardware designs that meet performance standards and integrate seamlessly into complex systems.

What are Design Engineer PCIe jobs?

Design Engineer PCIe jobs involve designing, developing, and testing hardware and systems that utilize PCI Express (PCIe) technology for high-speed data transfer. These engineers work on creating circuit boards, verifying PCIe interfaces, and ensuring compliance with industry standards. Their role often includes collaborating with software and hardware teams to optimize system integration and performance. Design Engineer PCIe professionals are crucial in industries like computing, networking, and storage solutions, where reliable and fast data communication is essential.

What is the difference between Design Engineer Pcie vs Design Engineer Usb?

AspectDesign Engineer PcieDesign Engineer Usb
Required SkillsPCIe protocol, hardware design, FPGA/ASIC developmentUSB standards, hardware design, FPGA/ASIC development
Work EnvironmentSemiconductor companies, hardware development labsConsumer electronics, peripheral device companies
CertificationsRelevant hardware design certifications, industry experienceSimilar certifications, focus on interface standards

Both Design Engineer Pcie and Design Engineer Usb roles involve hardware interface design, requiring similar skills and certifications. The main difference lies in the specific protocols and standards they work with: PCIe for high-speed data transfer in computers and servers, and USB for peripheral connectivity. Their work environments and industry applications also differ, with PCIe roles often in enterprise hardware and USB roles in consumer electronics.

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What states have the most Design Engineer Pcie jobs? States with the most job openings for Design Engineer Pcie jobs include:
What job categories do people searching Design Engineer Pcie jobs look for? The top searched job categories for Design Engineer Pcie jobs are:
Design Engineer Pcie jobs near you

SSD Qualification Engineer - PCIe Validation

Everpure

Santa Clara, CA • On-site

$180K - $270K/yr

Full-time

PTO

Posted 13 days ago

Job description

We're in an unbelievably exciting area of tech and are fundamentally reshaping the data storage industry. Here, you lead with innovative thinking, grow along with us, and join the smartest team in the industry.
This type of work-work that changes the world-is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us.
THE ROLE
As a PCIe Validation Engineer (IC) on the Drive Qualification team, you will design and execute PCIe-focused validation and debug for Everpure SSDs. You'll own link and protocol test coverage, develop automated test suites and frameworks using PCIe analyzers and exercisers, and drive issues from first detection through root cause and closure. This is a hands-on role with deep involvement in test development, lab debug, and cross-functional collaboration.
WHAT YOU'LL DO
  • Test Plans : Define PCIe test plans covering link training, lane width/speed changes, resets, hot-plug, surprise removal, error injection, power-management states, and recovery behaviour.
  • Execute PCIe validation Execute Gen4/Gen5/Gen6 link and protocol tests across different platforms and system configurations.Validate SSD behaviour under abnormal and corner conditions & provide periodic PCIe validation readouts for critical program milestones.
  • Develop PCIe test content & frameworks : Develop and maintain automated PCIe test suites, Integrate PCIe analyzers, exercisers, and Quarch-class tools into test frameworks to enable reproducible, automated scenarios.
  • Collaborate: Triage failures from regression, bring-up, and customer scenarios; correlate PCIe traces, NVMe/OCP logs, and system logs. Partner with FW, HW, and systems teams to root-cause and verify fixes, and roll improvements back into the test suite.
  • PCIe tools: Leverage PCIe analyzers/exercisers for trace capture, error injection. Use oscilloscopes, logic analyzers, BERTs, and related tools (as needed) to support signal- and protocol-level debug.
  • Test Roadmap & leadership: Lead coverage improvements based on lessons learned, standardize PCIe test APIs, logs, and reporting for reuse across products & share PCIe debug and test BKMs
  • We are primarily an in-office environment and therefore, you will be expected to work from the Santa Clara, CA office in compliance with Everpure's policies, unless you are on PTO, or work travel, or other approved leave.

WHAT YOU BRING
  • 6+ years experience in SSD, storage, or PCIe-centric validation / bring-up (or equivalent embedded / high-speed I/O domain).
  • Strong understanding of PCIe fundamentals:
  • Hands-on experience using PCIe analyzers/exercisers (e.g., Teledyne/LeCroy, Keysight, or similar) for trace capture and debug.
  • Comfortable with Python (or similar) for test and tooling development; able to work effectively in Linux-based validation environments.
  • Experience with CI / regression infrastructure (e.g., Jenkins, Git-based workflows) for large-scale test execution.
  • Strong debug skills across HW/FW/system boundaries; able to go from symptom to hypothesis to validated root cause.
  • Clear written and verbal communication, with the ability to present findings, trade-offs, and recommendations to engineering and program teams.
  • Highly self-motivated, detail-oriented, and comfortable operating in a fast-paced development environment.

#LI-ONSITE
Salary ranges are determined based on role, level and location. For positions open to candidates in multiple geographical locations, the base salary range is reflective of the labor market across the applicable locations.
This role may be eligible for incentive pay and/or equity.
There is no application deadline and we accept applications on an ongoing basis until the job is filled.
The annual base salary range is:
$180,000-$270,000 USD
WHAT YOU CAN EXPECT FROM US:
  • Innovation: We celebrate those who think critically, like a challenge, and aspire to be trailblazers.
  • Growth: We give you the space and support to grow along with us and to contribute to something meaningful. We have been named Fortune's Best Workplaces in Technology™, Fortune's Best Workplaces in the Bay Area™, and certified as a Great Place to Work®!
  • Team: We build each other up and set aside ego for the greater good.

And because we understand the value of bringing your full and best self to work, we offer a variety of perks to manage a healthy balance, including flexible time off, wellness resources, and company-sponsored team events. Check out purebenefits.com for more information.
ACCOMMODATIONS AND ACCESSIBILITY:
Candidates with disabilities may request accommodations for all aspects of our hiring process. For more on this, contact us at TA-Ops@purestorage.com if you're invited to an interview.
OUR COMMITMENT TO A STRONG AND INCLUSIVE TEAM:
We're forging a future where everyone finds their rightful place and where every voice matters. Where uniqueness isn't just accepted but embraced. That's why we are committed to fostering the growth and development of every person, cultivating a sense of community through our Employee Resource Groups and advocating for inclusive leadership.
Everpure is proud to be an equal opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or any other characteristic legally protected by the laws of the jurisdiction in which you are being considered for hire.
Join us and bring your best.
Bring your bold.
Pure and simple.

Apply