As a member of the front-end design/integration team, you will work closely with the architecture ... and firmware engineers to understand the new features to be verified for PCIe CXL based IP'
As a member of the front-end design/integration team, you will work closely with the architecture ... and firmware engineers to understand the new features to be verified for PCIe CXL based IP'
Principal PCIe Logic Design
Hillsboro, OR · On-site
$108 - $201/hr
... PCIe IP design team ... Candidates will be joining some of the brightest inventors and engineers in the world to develop ...
Principal PCIe Logic Design
Hillsboro, OR · On-site
$108 - $201/hr
... PCIe IP design team ... Candidates will be joining some of the brightest inventors and engineers in the world to develop ...
Principal PCIe Logic Design
Hillsboro, OR · Hybrid
$108K - $201K/yr
... PCIe IP design team ... Candidates will be joining some of the brightest inventors and engineers in the world to develop ...
Principal PCIe Logic Design
Hillsboro, OR · Hybrid
$108K - $201K/yr
... PCIe IP design team ... Candidates will be joining some of the brightest inventors and engineers in the world to develop ...
Hardware Design Engineer
Irvine, CA · On-site
... PCIe Gen4, 10G Ethernet Key Responsibilities High-Speed Digital Circuit Design and Board-Level ... Engineering Validation Testing (EVT), DVT, EMI/EMC, and Environmental Testing Field failure ...
Hardware Design Engineer
Irvine, CA · On-site
... PCIe Gen4, 10G Ethernet Key Responsibilities High-Speed Digital Circuit Design and Board-Level ... Engineering Validation Testing (EVT), DVT, EMI/EMC, and Environmental Testing Field failure ...
Principal PCIe Logic Design
Hillsboro, OR · On-site
$108K - $201K/yr
... PCIe IP design team ... Candidates will be joining some of the brightest inventors and engineers in the world to develop ...
Principal PCIe Logic Design
Hillsboro, OR · On-site
$108K - $201K/yr
... PCIe IP design team ... Candidates will be joining some of the brightest inventors and engineers in the world to develop ...
Digital Design Engineer
Endicott, NY · On-site
$129K/yr
Design of complex high speed digital circuit card assemblies including PCIe * Lead/Mentor a team of junior engineers * Support test and troubleshooting of systems, modules and sub-assemblies of ...
Digital Design Engineer
Endicott, NY · On-site
$129K/yr
Design of complex high speed digital circuit card assemblies including PCIe * Lead/Mentor a team of junior engineers * Support test and troubleshooting of systems, modules and sub-assemblies of ...
RTL Design Engineer - Specialized (US)
Santa Clara, CA · On-site
$95 - $100/hr
We are seeking an "RTL Design Engineer - Specialized " for one of our Semiconductor clients ... Having experience is Gbit high frequency design such as PCIe & Ethernet Phy design is a big plus.
Quick apply
RTL Design Engineer - Specialized (US)
Santa Clara, CA · On-site
$95 - $100/hr
We are seeking an "RTL Design Engineer - Specialized " for one of our Semiconductor clients ... Having experience is Gbit high frequency design such as PCIe & Ethernet Phy design is a big plus.
Design of complex high speed digital circuit card assemblies including PCIe * Lead/Mentor a team of junior engineers * Support test and troubleshooting of systems, modules and sub-assemblies of ...
Design of complex high speed digital circuit card assemblies including PCIe * Lead/Mentor a team of junior engineers * Support test and troubleshooting of systems, modules and sub-assemblies of ...
Hardware Design Engineer
Irvine, CA · On-site
... PCIe Gen4, 10G Ethernet Key Responsibilities: * High-Speed Digital Circuit Design and Board-Level ... Engineering Validation Testing (EVT), DVT, EMI/EMC, and Environmental Testing * Field failure ...
Hardware Design Engineer
Irvine, CA · On-site
... PCIe Gen4, 10G Ethernet Key Responsibilities: * High-Speed Digital Circuit Design and Board-Level ... Engineering Validation Testing (EVT), DVT, EMI/EMC, and Environmental Testing * Field failure ...
Hardware Design Engineer
Irvine, CA · On-site
... PCIe Gen4, 10G Ethernet Key Responsibilities * High-Speed Digital Circuit Design and Board-Level ... Engineering Validation Testing (EVT), DVT, EMI/EMC, and Environmental Testing * Field failure ...
Hardware Design Engineer
Irvine, CA · On-site
... PCIe Gen4, 10G Ethernet Key Responsibilities * High-Speed Digital Circuit Design and Board-Level ... Engineering Validation Testing (EVT), DVT, EMI/EMC, and Environmental Testing * Field failure ...
Principal PCIe Logic Design
Hillsboro, OR · Hybrid
$108K - $201K/yr
... PCIe IP design team ... Candidates will be joining some of the brightest inventors and engineers in the world to develop ...
Principal PCIe Logic Design
Hillsboro, OR · Hybrid
$108K - $201K/yr
... PCIe IP design team ... Candidates will be joining some of the brightest inventors and engineers in the world to develop ...
Staff Logic Design Engineer
Milpitas, CA · On-site
$141K - $189K/yr
Integrate PCIe IP cores, DMA engines, and custom protocol decoders. * Verification & Debug * Build ... design practices. Required Qualifications * BS in EE, CS or Computer Engineering required * MS in ...
Staff Logic Design Engineer
Milpitas, CA · On-site
$141K - $189K/yr
Integrate PCIe IP cores, DMA engines, and custom protocol decoders. * Verification & Debug * Build ... design practices. Required Qualifications * BS in EE, CS or Computer Engineering required * MS in ...
Principal PCIe Subsystem RTL lead
San Jose, CA · On-site
$180 - $240/hr
Mentor and guide RTL design engineers responsible for PCIe subsystem implementation, providing architectural guidance and RTL review. * Partner with the DV team to define the PCIe UVM verification ...
Principal PCIe Subsystem RTL lead
San Jose, CA · On-site
$180 - $240/hr
Mentor and guide RTL design engineers responsible for PCIe subsystem implementation, providing architectural guidance and RTL review. * Partner with the DV team to define the PCIe UVM verification ...
Staff Logic Design Engineer
Milpitas, CA · On-site
$141K - $189K/yr
Integrate PCIe IP cores, DMA engines, and custom protocol decoders. * Verification & Debug * Build ... design practices. Required Qualifications * BS in EE, CS or Computer Engineering required * MS in ...
Staff Logic Design Engineer
Milpitas, CA · On-site
$141K - $189K/yr
Integrate PCIe IP cores, DMA engines, and custom protocol decoders. * Verification & Debug * Build ... design practices. Required Qualifications * BS in EE, CS or Computer Engineering required * MS in ...
Staff Logic Design Engineer (Milpitas)
Milpitas, CA · On-site
$141K - $189K/yr
Staff Logic Design Engineer page is loaded## Staff Logic Design Engineerlocations: US - Milpitas ... You'll work on FPGA-based systems that decode and analyze High speed protocols (PCIe, USB, Ethernet ...
Staff Logic Design Engineer (Milpitas)
Milpitas, CA · On-site
$141K - $189K/yr
Staff Logic Design Engineer page is loaded## Staff Logic Design Engineerlocations: US - Milpitas ... You'll work on FPGA-based systems that decode and analyze High speed protocols (PCIe, USB, Ethernet ...
Analog Design Engineer
Endicott, NY · On-site
$192K/yr
... as PCIe, SPI, I2C, UART, GPIO, DDR, Ethernet, ARINC, 1553, etc. * Design, simulation, and ... Work closely with PWB packaging and layout engineers * Generate and review engineering ...
Quick apply
Analog Design Engineer
Endicott, NY · On-site
$192K/yr
... as PCIe, SPI, I2C, UART, GPIO, DDR, Ethernet, ARINC, 1553, etc. * Design, simulation, and ... Work closely with PWB packaging and layout engineers * Generate and review engineering ...
Principal PCIe Subsystem RTL lead
San Jose, CA · On-site
$159K - $164K/yr
Mentor and guide RTL design engineers responsible for PCIe subsystem implementation, providing architectural guidance and RTL review. * Partner with the DV team to define the PCIe UVM verification ...
Principal PCIe Subsystem RTL lead
San Jose, CA · On-site
$159K - $164K/yr
Mentor and guide RTL design engineers responsible for PCIe subsystem implementation, providing architectural guidance and RTL review. * Partner with the DV team to define the PCIe UVM verification ...
PCB Design Engineer
Austin, TX · On-site
PCB Design Engineer Type/Duration: Full time//Permanent Location: Austin, TX (5 Days onsite in a ... Knowledge on High speed interfaces such (SATA, DDR4, DDR5, USB, Ethernet, PCIe, PMIC etc)
New
PCB Design Engineer
Austin, TX · On-site
PCB Design Engineer Type/Duration: Full time//Permanent Location: Austin, TX (5 Days onsite in a ... Knowledge on High speed interfaces such (SATA, DDR4, DDR5, USB, Ethernet, PCIe, PMIC etc)
New
Senior Hardware Design Engineer
Newark, CA · On-site
$130K - $150K/yr
Senior Hardware Design Engineer Reports To: Sr. Director, Hardware & Systems Engineering Job ... and PCIe Gen 5/6. * Power & Signal Integrity: Define and optimize robust board-level power ...
Quick apply
Senior Hardware Design Engineer
Newark, CA · On-site
$130K - $150K/yr
Senior Hardware Design Engineer Reports To: Sr. Director, Hardware & Systems Engineering Job ... and PCIe Gen 5/6. * Power & Signal Integrity: Define and optimize robust board-level power ...
Analog Design Engineer
$206K/yr
... PCIe, SPI, I2C, UART, GPIO, DDR, Ethernet, ARINC, 1553, etc.) • High-speed interface design and ... Engineering, Operations, and Quality teams for defect resolution • Drive design and process ...
Analog Design Engineer
$206K/yr
... PCIe, SPI, I2C, UART, GPIO, DDR, Ethernet, ARINC, 1553, etc.) • High-speed interface design and ... Engineering, Operations, and Quality teams for defect resolution • Drive design and process ...
Design Engineer Pcie information
See salary details
$40.5K - $51.2K
2% of jobs
$51.2K - $62K
11% of jobs
$67.7K is the 25th percentile. Wages below this are outliers.
$62K - $72.7K
23% of jobs
The median wage is $79.6K / yr.
$72.7K - $83.4K
22% of jobs
$83.4K - $94.1K
17% of jobs
$94.4K is the 75th percentile. Wages above this are outliers.
$94.1K - $104.9K
9% of jobs
$104.9K - $115.6K
6% of jobs
$115.6K - $126.3K
3% of jobs
$126.3K - $137K
3% of jobs
$137K - $147.8K
2% of jobs
$147.8K - $158.5K
1% of jobs
$40.5K
$88.2K
$158.5K
How much do design engineer pcie jobs pay per year?
What is a design engineer PCIe?
What are some typical challenges a design engineer PCIe faces when integrating PCIe interfaces into new hardware products?
What are the key skills and qualifications needed to thrive as a design engineer PCIe, and why are they important?
What is the difference between Design Engineer Pcie vs Design Engineer Usb?
| Aspect | Design Engineer Pcie | Design Engineer Usb |
|---|---|---|
| Required Skills | PCIe protocol, hardware design, FPGA/ASIC development | USB standards, hardware design, FPGA/ASIC development |
| Work Environment | Semiconductor companies, hardware development labs | Consumer electronics, peripheral device companies |
| Certifications | Relevant hardware design certifications, industry experience | Similar certifications, focus on interface standards |
Both Design Engineer Pcie and Design Engineer Usb roles involve hardware interface design, requiring similar skills and certifications. The main difference lies in the specific protocols and standards they work with: PCIe for high-speed data transfer in computers and servers, and USB for peripheral connectivity. Their work environments and industry applications also differ, with PCIe roles often in enterprise hardware and USB roles in consumer electronics.
What cities are hiring for Design Engineer Pcie jobs?
Cities with the most Design Engineer Pcie job openings:
What states have the most Design Engineer Pcie jobs?
States with the most job openings for Design Engineer Pcie jobs include:
What job categories do people searching Design Engineer Pcie jobs look for?
The top searched job categories for Design Engineer Pcie jobs are:

Full-time
Posted 4 days ago
Advanced Micro Devices rating
8.6
Based on 13 frontline employees who took The Breakroom Quiz
27th of 159 rated electronics manufacturers
Job description
ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.
AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.
THE ROLE:
As a Senior ASIC Verification Engineer, you will help bring to life cutting-edge FPGA, ASICs for variety of target customers.As a member of the front-end design/integration team, you will work closely with the architecture, IP design, PD teams, and product engineers to achieve first pass silicon success.
THE PERSON:
You have a passion for modern, complex IP architectures, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBLITIES:
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified for PCIe CXL based IP's
- Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Code IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers
- Build the directed and random verification tests
- Run regressions, debug test failures towards ensuring high design functional, performance and implementation quality
PREFERRED EXPERIENCE:
- Experience with PCIe or CXL or NVMe or ethernet protocols is a must
- Proficient in IP level ASIC verification
- Expert in Verilog, System Verilog, Object Oriented programming
- Expertise in developing UVM based verification frameworks and testbenches
- Scripting and automation of verification processes and flows
- Exposure to leadership or mentorship is an asset
- Experience working in a team environment through the ASIC / FPGA Project lifecycle from Planning to Tape Out
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Good Computer Architecture, systems knowledge
- Comfortable in python / perl and editing / maintaining scripts
- Strong communication skills and the ability to work independently as well as in a cross-site team environment
- Exposure to generative AI or simulation tools for test, testbench, assertion, test plan generation or performance optimization is a plus
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
LOCATION:
- San Jose, CA,
- Candidates located in San Diego, CA; Austin, TX; or Longmont, CO may be considered for more senior-level experienced candidates.
This role is not eligible for visa sponsorship.
#LI-EV1
#LI-HYBRID
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Qualifications:Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Education:UNAVAILABLEEmployment Type: FULL_TIMEWhat Advanced Micro Devices employees say
Pay
Benefits
Hours and flexibility
Workplace
Get the full story on Breakroom
About Advanced Micro Devices (AMD)
Sourced by ZipRecruiter
Industry
Computer and electronic product manufacturing and manufacturing
Company size
5,001 - 10,000 Employees
Headquarters location
Sunnyvale, CA, US