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Design Engineer Pcie Jobs (NOW HIRING)

... PCIe Gen4, 10G Ethernet Key Responsibilities High-Speed Digital Circuit Design and Board-Level ... Engineering Validation Testing (EVT), DVT, EMI/EMC, and Environmental Testing Field failure ...

Staff Logic Design Engineer

Milpitas, CA · On-site

$141K - $189K/yr

Integrate PCIe IP cores, DMA engines, and custom protocol decoders. * Verification & Debug * Build ... design practices. Required Qualifications * BS in EE, CS or Computer Engineering required * MS in ...

Mentor and guide RTL design engineers responsible for PCIe subsystem implementation, providing architectural guidance and RTL review. * Partner with the DV team to define the PCIe UVM verification ...

Staff Logic Design Engineer

Milpitas, CA · On-site

$141K - $189K/yr

Integrate PCIe IP cores, DMA engines, and custom protocol decoders. * Verification & Debug * Build ... design practices. Required Qualifications * BS in EE, CS or Computer Engineering required * MS in ...

Analog Design Engineer

Endicott, NY · On-site

$192K/yr

... as PCIe, SPI, I2C, UART, GPIO, DDR, Ethernet, ARINC, 1553, etc. * Design, simulation, and ... Work closely with PWB packaging and layout engineers * Generate and review engineering ...

Principal PCIe Subsystem RTL lead

San Jose, CA · On-site

$159K - $164K/yr

Mentor and guide RTL design engineers responsible for PCIe subsystem implementation, providing architectural guidance and RTL review. * Partner with the DV team to define the PCIe UVM verification ...

PCB Design Engineer Type/Duration: Full time//Permanent Location: Austin, TX (5 Days onsite in a ... Knowledge on High speed interfaces such (SATA, DDR4, DDR5, USB, Ethernet, PCIe, PMIC etc)

New

Senior Hardware Design Engineer Reports To: Sr. Director, Hardware & Systems Engineering Job ... and PCIe Gen 5/6. * Power & Signal Integrity: Define and optimize robust board-level power ...

Analog Design Engineer

$206K/yr

... PCIe, SPI, I2C, UART, GPIO, DDR, Ethernet, ARINC, 1553, etc.) • High-speed interface design and ... Engineering, Operations, and Quality teams for defect resolution • Drive design and process ...

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Design Engineer Pcie information

See salary details

$40.5K

$88.2K

$158.5K

How much do design engineer pcie jobs pay per year?

As of Aug 22, 2026, the average yearly pay for design engineer pcie in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.

What is a design engineer PCIe?

Design Engineer PCIe jobs involve designing, developing, and testing hardware and systems that utilize PCI Express (PCIe) technology for high-speed data transfer. These engineers work on creating circuit boards, verifying PCIe interfaces, and ensuring compliance with industry standards. Their role often includes collaborating with software and hardware teams to optimize system integration and performance. Design Engineer PCIe professionals are crucial in industries like computing, networking, and storage solutions, where reliable and fast data communication is essential.

What are some typical challenges a design engineer PCIe faces when integrating PCIe interfaces into new hardware products?

As a Design Engineer PCIe, you will often encounter challenges related to ensuring signal integrity and compatibility when integrating PCIe interfaces into hardware designs. This can involve addressing issues like high-speed signal routing, managing power consumption, and ensuring compliance with PCIe standards. Collaboration with firmware, hardware, and verification teams is common to resolve interoperability issues and optimize performance. Staying updated on the latest PCIe specifications and debugging complex system-level problems are also key aspects of the role.

What are the key skills and qualifications needed to thrive as a design engineer PCIe, and why are they important?

To excel as a Design Engineer specializing in PCIe, you need a solid background in electrical or computer engineering, with expertise in high-speed digital design and thorough knowledge of PCI Express protocols. Proficiency with hardware design tools such as Cadence or Synopsys, simulation tools, and familiarity with industry standards like PCIe specifications are typically required. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help set top engineers apart. These competencies ensure robust, reliable hardware designs that meet performance standards and integrate seamlessly into complex systems.

What is the difference between Design Engineer Pcie vs Design Engineer Usb?

AspectDesign Engineer PcieDesign Engineer Usb
Required SkillsPCIe protocol, hardware design, FPGA/ASIC developmentUSB standards, hardware design, FPGA/ASIC development
Work EnvironmentSemiconductor companies, hardware development labsConsumer electronics, peripheral device companies
CertificationsRelevant hardware design certifications, industry experienceSimilar certifications, focus on interface standards

Both Design Engineer Pcie and Design Engineer Usb roles involve hardware interface design, requiring similar skills and certifications. The main difference lies in the specific protocols and standards they work with: PCIe for high-speed data transfer in computers and servers, and USB for peripheral connectivity. Their work environments and industry applications also differ, with PCIe roles often in enterprise hardware and USB roles in consumer electronics.

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Infographic showing various Design Engineer Pcie job openings in the United States as of August 2026, with employment types broken down into 89% Full Time, 7% Part Time, and 4% Contract. Highlights an 83% Physical, 5% Hybrid, and 12% Remote job distribution, with an average salary of $88,150 per year, or $42.4 per hour.

Senior ASIC Verification Engineer (PCIe/CXL)

Advanced Micro Devices, Inc

San Jose, CA • Hybrid

Full-time

Posted 4 days ago


Advanced Micro Devices rating

8.6

Company rating: 8.6 out of 10

Based on 13 frontline employees who took The Breakroom Quiz

27th of 159 rated electronics manufacturers


Job description


ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.



THE ROLE: 

As a Senior ASIC Verification Engineer, you will help bring to life cutting-edge FPGA, ASICs for variety of target customers.As a member of the front-end design/integration team, you will work closely with the architecture, IP design, PD teams, and product engineers to achieve first pass silicon success.


THE PERSON:

You have a passion for modern, complex IP architectures, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

KEY RESPONSIBLITIES:

  • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified for PCIe CXL based IP's
  • Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
  • Code IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers
  • Build the directed and random verification tests 
  • Run regressions, debug test failures towards ensuring high design functional, performance and implementation quality 

PREFERRED EXPERIENCE:

  • Experience with PCIe or CXL or NVMe or ethernet protocols is a must 
  • Proficient in IP level ASIC verification 
  • Expert in Verilog, System Verilog, Object Oriented programming
  • Expertise in developing UVM based verification frameworks and testbenches
  • Scripting and automation of verification processes and flows 
  • Exposure to leadership or mentorship is an asset 
  • Experience working in a team environment through the ASIC / FPGA Project lifecycle from Planning to Tape Out
  • Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
  • Good Computer Architecture, systems knowledge
  • Comfortable in python / perl and editing / maintaining scripts
  • Strong communication skills and the ability to work independently as well as in a cross-site team environment
  • Exposure to generative AI  or simulation tools for test, testbench, assertion, test plan generation or performance optimization is a plus

ACADEMIC CREDENTIALS:

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 

LOCATION: 

  • San Jose, CA,
  • Candidates located in San Diego, CA; Austin, TX; or Longmont, CO may be considered for more senior-level experienced candidates. 

This role is not eligible for visa sponsorship.

#LI-EV1

#LI-HYBRID 



Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

Qualifications:

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

Education:UNAVAILABLEEmployment Type: FULL_TIME

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