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Principal Verification Engineer Jobs in California

Skyworks

Sr. Principal AMS Verification Engineer

Irvine, CA · On-site

$143K - $286K/yr

Sr. Principal AMS Verification Engineer Posting Start Date: 6/15/26 Job Location(s): Austin, Cedar Rapids, Irvine, Newbury Park, San Jose If you are looking for a challenging and exciting career in ...

Nokia

Principal ASIC verification Engineer

San Jose, CA · On-site

Principal Design Engineer: M.S. in E.E. with 12+ years' experience, or Ph.D. in E.E. with 8+ years ... Perform the functional verification and timing analysis on the IPs and the blocks. * Work with the ...

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Showing results 21-40

All JobsPrincipal Verification Engineer JobsPrincipal Verification Engineer Jobs in California

Principal Verification Engineer information

See California salary details

$73K

$145.3K

$209.7K

How much do principal verification engineer jobs pay per year?

As of Aug 7, 2026, the average yearly pay for principal verification engineer in California is $145,292.00, according to ZipRecruiter salary data. Most workers in this role earn between $116,900.00 and $170,700.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a principal verification engineer?

A Principal Verification Engineer needs deep expertise in digital design, verification methodologies (such as UVM or SystemVerilog), and a degree in electrical or computer engineering. Mastery of simulation tools (like ModelSim or VCS), scripting languages (Perl, Python), and familiarity with hardware description languages are typically required. Exceptional problem-solving, leadership, and communication skills help in leading teams and collaborating across engineering functions. These competencies ensure rigorous product validation, efficient project execution, and high-quality semiconductor or hardware releases.

What is a principal verification engineer?

A Principal Verification Engineer is a senior-level professional responsible for leading the verification process of complex hardware or software systems, ensuring that designs meet all specifications and functional requirements. They develop and implement verification strategies, create test plans, and oversee the execution of simulation and validation activities. Principal Verification Engineers often mentor junior engineers, collaborate with design and architecture teams, and play a key role in identifying and resolving critical design issues. Their work is essential for delivering high-quality, reliable products in industries such as semiconductor, electronics, and automotive. This role typically requires extensive experience in verification methodologies and strong problem-solving skills.

What are some common challenges faced by a principal verification engineer, and how can they be addressed?

Principal Verification Engineers often navigate complex verification environments, tight project timelines, and coordination across multiple teams. A key challenge is ensuring comprehensive test coverage while managing evolving design specifications. Effective communication with design and firmware teams, proactive identification of verification gaps, and leveraging advanced verification methodologies (such as constrained-random testing and formal verification) can help address these challenges. Additionally, mentoring junior engineers and fostering a culture of knowledge sharing are vital for team success.

What is the difference between Principal Verification Engineer vs Verification Engineer?

AspectPrincipal Verification EngineerVerification Engineer
CredentialsTypically requires a Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields; extensive experience in verification methodologiesUsually holds a Bachelor's or Master's in a relevant engineering discipline; less extensive experience needed
Work EnvironmentLeads verification teams, designs verification strategies, and oversees complex projectsPerforms verification tasks, runs tests, and documents results under supervision
Industry UsageCommonly found in semiconductor, electronics, and hardware industriesWidely used across similar industries for testing and validation roles

The Principal Verification Engineer typically has more experience, leadership responsibilities, and oversees verification processes, while Verification Engineers focus on executing tests and validating designs. Both roles are essential in ensuring product quality but differ in scope and seniority.

What are popular job titles related to Principal Verification Engineer jobs in California? For Principal Verification Engineer jobs in California, the most frequently searched job titles are:
What job categories do people searching Principal Verification Engineer jobs in California look for? The top searched job categories for Principal Verification Engineer jobs in California are:
Principal Verification Engineer jobs near you
Infographic showing various Principal Verification Engineer job openings in California as of August 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $145,292 per year, or $69.9 per hour.

Principal Design Verification Engineer

Bolt Graphics

Sunnyvale, CA • On-site

$250K - $280K/yr

Full-time

Medical, Dental, Vision, Retirement

Re-posted 23 days ago

Job description

Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.
Our Values
  • Be Fearless: Unmute yourself. Test boundaries and get proven right.
  • Remain Adaptable: Stay comfortable in a continuously changing world. If you're wrong, concede and move on.
  • Educate Your Ego: Selflessly collaborate towards our shared purpose.

About the role:
As a Principal Design Verification Engineer, you will own the verification strategy and execution for complex IPs or full-chip SoC. You will lead a team of verification engineers, define methodologies, drive coverage closure, and ensure high-quality silicon delivery. This is an on-site role and will require presence in the office 5 days a week. No hybrid option is available.
What you'll do:
Leadership & Strategy
  • Define and drive end-to-end verification strategy (block → subsystem → full-chip)
  • Build, mentor, and scale a high-performing DV team
  • Establish verification plans, milestones, and coverage goals
  • Drive alignment across architecture, RTL, and physical design teams

Verification Execution
  • Lead development of UVM-based verification environments
  • Define testbench architecture, stimulus strategy, and reusable components
  • Drive functional, code, and assertion coverage closure
  • Oversee regression infrastructure, debug, and signoff criteria

Advanced Verification & Signoff
  • Drive GLS (Gate-Level Simulation) with SDF annotation and timing-aware debug
  • Manage low-power verification (UPF/CPF) and power-aware simulation
  • Oversee formal verification, linting, CDC/RDC analysis
  • Ensure robust reset, clocking, and cross-domain verification

Cross-Functional Collaboration
  • Work with RTL teams on design-for-verification (DFV) improvements
  • Collaborate with PD teams on timing-related verification issues
  • Support post-silicon bring-up and debug
  • Interface with customers/partners on verification readiness and quality

Required Qualifications:
  • Bachelor's/Master's degree in Electrical Engineering or related field
  • 12-15 years of experience in ASIC/SoC design verification
  • Proven experience leading verification teams and delivering multiple tapeouts
  • Strong expertise in:
    • SystemVerilog and UVM methodology
    • Functional coverage, assertions (SVA), and constrained-random verification
    • Debugging complex SoC-level issues
  • Hands-on experience with industry-standard tools such as:
    • Synopsys VCS / Cadence Xcelium
    • Synopsys Verdi
  • Strong understanding of:
    • Clock/reset domain crossings (CDC/RDC)
    • Low-power verification methodologies
    • Gate-level simulation and SDF annotation
  • Excellent leadership, communication, and problem-solving skills

Preferred Qualifications:
  • Experience in CPU/GPU/AI/Networking SoCs
  • Expertise in GLS debug (X-propagation, SDF issues, timing failures)
  • Familiarity with emulation platforms (e.g., Synopsys ZeBu)
  • Experience with post-silicon validation and bring-up
  • Knowledge of performance verification and system-level validation
  • Strong scripting skills (Python/TCL) for automation and regression scaling

Compensation Range: $250,000-$280,000 per year (California). This range represents the anticipated base pay for this role based in California; the final offer may vary based on qualifications, experience, and location.
Benefits:
  • Medical, Dental, & Vision - 100% covered premiums
  • Equity - Stock Options
  • 401(k) match
  • WFH Hardware

Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other's differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.

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