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Ic Layout Jobs (NOW HIRING)

Glow Networks

Analog Layout Engineer

Santa Clara, CA · On-site

$237K/yr

Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 5nm, 7nm, 16nm, 28nm, 40nm and 65nm following best ...

SpaceX

RFIC Layout Designer (RFIC Engineering)

Redmond, WA · On-site

$120K - $175K/yr

You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and ...

SRI International

Analog IC Design Engineer

Princeton, NJ · On-site

$81K - $108K/yr

Experience in analog IC layout to address DRC, LVS, matching, shielding, electromigration, IR drops, and power/ground bouncing issues * Design and tape-out experience of analog and mixed-signal CMOS ...

SRI International

Analog IC Design Engineer

Princeton, NJ · On-site

$81K - $108K/yr

Experience in analog IC layout to address DRC, LVS, matching, shielding, electromigration, IR drops, and power/ground bouncing issues * Design and tape-out experience of analog and mixed-signal CMOS ...

SpaceX

RFIC Layout Designer (RFIC Engineering)

Redmond, WA · On-site

$120K - $175K/yr

You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and ...

SpaceX

RFIC Layout Designer (RFIC Engineering)

Irvine, CA · On-site

$120K - $170K/yr

You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and ...

MACOM Technology Solutions Holdings

$60K - $96K/yr

Lead full-custom IC layout design and verification, including chip floor planning, analog IP layout and chip level layout integration of various analog, mixed signal and ASIC blocks * Full ...

NuByt, Inc

Be Seen First

Analog Layout Engineer

San Jose, CA · On-site

$90 - $95/hr

The ideal candidate will have strong hands-on experience with analog IC layout, advanced process technologies, physical verification, and layout optimization. Responsibilities * Perform layout of ...

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How much do ic layout jobs pay per hour?

As of Aug 12, 2026, the average hourly pay for ic layout in the United States is $21.83, according to ZipRecruiter salary data. Most workers in this role earn between $15.62 and $22.12 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive in the IC layout position, and why are they important?

To thrive as an IC Layout professional, you need strong proficiency in analog and digital integrated circuit (IC) layout design, a solid understanding of semiconductor physics, and a degree in electrical engineering or a related field. Expertise with Electronic Design Automation (EDA) tools such as Cadence Virtuoso, Mentor Graphics, or Synopsys is typically required. Attention to detail, effective communication, and the ability to collaborate with circuit design engineers are valuable soft skills. These qualities ensure that layouts are precise, manufacturable, and meet stringent performance and reliability standards in the semiconductor industry.

What are some common challenges faced by IC layout engineers, and how do they typically overcome them?

IC Layout engineers often encounter challenges such as balancing area constraints with performance requirements, minimizing parasitic effects, and ensuring adherence to complex design rules. These challenges are addressed by leveraging advanced EDA tools, closely collaborating with circuit designers to understand specific needs, and frequently reviewing and updating the layout to align with fabrication requirements. Strong analytical thinking and attention to detail are essential for identifying and solving these issues. By keeping up with evolving technology and continually honing their skills, IC Layout engineers can efficiently deliver robust and high-quality designs.

What is an IC layout?

An IC Layout job involves designing the physical layout of integrated circuits (ICs) to ensure they meet electrical, manufacturing, and performance requirements. Layout engineers use specialized software to place and route transistors, resistors, and metal interconnects while following design rules and constraints. They work closely with circuit designers to optimize the layout for power, performance, and area. The role requires knowledge of semiconductor manufacturing processes and layout verification techniques such as DRC (Design Rule Checking) and LVS (Layout vs. Schematic).

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Ic Layout jobs near you
Infographic showing various Ic Layout job openings in the United States as of July 2026, with employment types broken down into 87% Full Time, 8% Part Time, 2% Contract, and 3% Nights. Highlights an 95% Physical, 1% Hybrid, and 4% Remote job distribution, with an average salary of $45,402 per year, or $21.8 per hour.

Analog Layout Engineer

Glow Networks

Santa Clara, CA • On-site

$237K/yr

Full-time

Re-posted 4 days ago

Job description

Role: Analog Layout Engineer
Location: Santa Clara, CA (Remote Option available)
Duration: Long Term
Responsibilities:
Senior layout designer, will be responsible for layout of high-performance analog cores such as analog-to-digital converters, digital-to-analog converters, PLL, transceivers, etc.
Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 5nm, 7nm, 16nm, 28nm, 40nm and 65nm following best practices from the industry.
Qualifications
Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys.
Must be able to set up LVS, DRC, ERC environments and debug verification issues using Cadence and Mentor tools.
Experience with layout of high-performance analog blocks such as analog to digital converters, references, digital to analog converters, PLL etc. desired.
Experience with floor planning, block level routing and top-level chip assembly.
Knowledge of high-performance analog layout techniques such as common centroid layout, shielding, use of dummy devices, thermal aware layout with consideration for electromigration.
Demonstrated experience with analog layout for silicon chips in mass production.
Experience with FinFET process nodes preferred
Experience working with distributed design teams a plus.
Knowledge of skill code and layout automation is a plus.
Self-starter with the ability to define and adhere to a schedule.
Must possess strong written and verbal communication skills.
10+ years' experience in high performance analog layout in advanced CMOS processes.

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