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Ic Mask Designer Jobs (NOW HIRING)

Neuralink

Analog IC Layout Engineer

Fremont, CA

You will have the opportunity to collaborate closely with chip designers, electrical engineers ... Physical verification of custom IC mask layouts (LVS, DRC, ERC) Required Qualifications: * 2+ years ...

Neuralink

Analog IC Layout Engineer

Fremont, CA · On-site

$83K - $139K/yr

You will have the opportunity to collaborate closely with chip designers, electrical engineers ... Physical verification of custom IC mask layouts (LVS, DRC, ERC) Required Qualifications: * 2+ years ...

Texas Instruments

Layout Designer

Tucson, AZ

... Advanced IC Mask Layout Design * Minimum of 5 years of experience. Preferred qualifications ... We offer competitive pay and benefits designed to help you and your family live your best life.

Texas Instruments

Layout Designer

Tucson, AZ

Texas Instruments is seeking an experienced Layout Designer to join our team! Responsibilities ... Advanced IC Mask Layout Design * Minimum of 5 years of experience. Preferred qualifications:

Texas Instruments

Layout Designer

Tucson, AZ

... Advanced IC Mask Layout Design * Minimum of 5 years of experience. Preferred qualifications ... We offer competitive pay and benefits designed to help you and your family live your best life.

Apple

IC Designer - Power Management

Cupertino, CA · On-site

... with mask design to construct layout collaterals. • Navigate through optimizations of power, area and performance or power IC designs. • Develop subcell and IP-level simulations to validate ...

Texas Instruments

Layout Designer

Tucson, AZ · On-site

... Advanced IC Mask Layout Design * Minimum of 5 years of experience. Preferred qualifications ... We offer competitive pay and benefits designed to help you and your family live your best life.

Apple

IC Designer - Power Management

Cupertino, CA

$172.10K - $305.60K/yr

... mask design to construct layout collaterals. • Navigate through optimizations of power, area and performance or power IC designs. • Develop subcell and IP-level simulations to validate designs ...

Apple

Analog IC Design Engineer

Cupertino, CA · On-site

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... as it applies to analog IC designsProven working experience in using spectrum analyzers ...

Apple

Analog IC Design Engineer

Cupertino, CA · On-site

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... as it applies to analog IC designsProven working experience in using spectrum analyzers ...

Apple

Analog IC Design Engineer

Cupertino, CA · On-site

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... as it applies to analog IC designsProven working experience in using spectrum analyzers ...

Apple

Analog IC Design Engineer

Cupertino, CA · On-site

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... as it applies to analog IC designsProven working experience in using spectrum analyzers ...

Apple

Analog IC Design Engineer

Cupertino, CA · On-site

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... as it applies to analog IC designsProven working experience in using spectrum analyzers ...

Apple

Analog IC Design Engineer

Cupertino, CA

$181.10K - $318.40K/yr

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...

Apple

Analog IC Design Engineer

Cupertino, CA

$181.10K - $318.40K/yr

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...

Apple

Analog IC Design Engineer

Cupertino, CA

$126.80K - $220.90K/yr

Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...

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Ic Mask Designer information

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$150K

$175K

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How much do ic mask designer jobs pay per year?

As of Jun 1, 2026, the average yearly pay for ic mask designer in the United States is $175,000.00, according to ZipRecruiter salary data. Most workers in this role earn between $162,500.00 and $187,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an IC Mask Designer, and why are they important?

To thrive as an IC Mask Designer, you need a strong background in semiconductor physics, layout design principles, and typically a degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools such as Cadence Virtuoso, Mentor Graphics, and knowledge of DRC/LVS verification systems is essential. Attention to detail, problem-solving ability, and effective communication are important soft skills in this role. These skills ensure the creation of accurate, manufacturable mask layouts, reducing errors and supporting efficient chip fabrication.

What are some common challenges IC Mask Designers face when collaborating with circuit design and layout teams?

IC Mask Designers often work closely with circuit design and layout teams, and one common challenge is ensuring that design intent is accurately translated into the physical layout while adhering to stringent manufacturing rules. Communication is crucial, as mask designers must clarify any ambiguities in circuit schematics and collaborate to resolve design-for-manufacturability issues. Balancing performance, area constraints, and yield optimization requires continuous feedback and coordination, especially when dealing with tight project timelines and last-minute design changes.

What are IC Mask Designers?

IC Mask Designers are specialized engineers or technicians who create the photomasks used in the fabrication of integrated circuits (ICs). They translate complex circuit schematics into detailed layouts that define where various components and connections will be placed on a silicon wafer. Using advanced computer-aided design (CAD) tools, IC Mask Designers ensure the accuracy and manufacturability of these layouts, which are critical for producing high-performance and reliable semiconductor devices. Their work is essential in the semiconductor industry, as errors in mask design can lead to costly fabrication issues.

What is the difference between Ic Mask Designer vs IC Process Engineer?

AspectIC Mask DesignerIC Process Engineer
Required CredentialsTypically a degree in Electrical Engineering, Microelectronics, or related field; familiarity with CAD toolsDegree in Chemical, Electrical, or Materials Engineering; knowledge of fabrication processes
Work EnvironmentDesign labs, cleanrooms, CAD software environmentsManufacturing facilities, cleanrooms, process development labs
Industry UsageDesigning photomasks for semiconductor fabricationDeveloping and optimizing semiconductor manufacturing processes
Common Search/ComparisonIC Mask Designer vs IC Process Engineer

The IC Mask Designer focuses on creating detailed photomask layouts used in semiconductor fabrication, requiring expertise in CAD tools and design principles. In contrast, the IC Process Engineer works on developing and refining manufacturing processes to produce semiconductors efficiently. Both roles are essential in the semiconductor industry but differ in their focus—design versus process development.

More about Ic Mask Designer jobs
What states have the most Ic Mask Designer jobs? States with the most job openings for Ic Mask Designer jobs include:
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Ic Mask Designer jobs near you
Infographic showing various Ic Mask Designer job openings in the United States as of May 2026, with employment types broken down into 1% Internship, 83% Full Time, 11% Part Time, and 5% Contract. Highlights an 94% Physical, and 6% Hybrid job distribution, with an average salary of $175,000 per year, or $84.1 per hour.
Analog IC Layout Engineer

Analog IC Layout Engineer

Neuralink

Fremont, CA

Other

Posted 3 days ago

Job description

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description and Responsibilities:

We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer, your responsibilities will include:

  • Crafting state-of-the-art layouts for mixed-signal and analog circuits
    • Amplifiers
    • Filters
    • Switched capacitor circuits
    • Oscillators
    • Data converters
    • Power management circuits
  • Reviewing layout floorplans and analyzing high-fidelity circuits with circuit engineers
  • Physical verification of custom IC mask layouts (LVS, DRC, ERC)

Required Qualifications:

  • 2+ years of experience in analog and mixed-signal IC layout design
  • 1+ year experience with FinFET technologies
  • Ability to identify the best approach to solving problems

Preferred Qualifications:

  • Programming/scripting knowledge in SKILL, TCL, Shell, C/C++, and/or Python
  • Proven expertise in implementing analog and mixed-signal layout designs, achieving tight matching, low noise, and low power consumption
  • Understanding on failure-prone circuit and layout structures
  • Experience with analog DFM standards
  • Experience with layout P-cell design and implementation
  • Experience with layout automation 

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