You will work as a team with layout designers and engineers, local and/or globally to complete full chip projects. Responsibilities include all aspects of IC mask design from creating full chip floor ...
You will work as a team with layout designers and engineers, local and/or globally to complete full chip projects. Responsibilities include all aspects of IC mask design from creating full chip floor ...
Leverage Top-Down Bottom-Up (TDBU) floorplan methodology to create and refine the RFID or Reader IC floorplan - collaborating with circuit and block-level layout designers on sizing, pin rings, inter ...
Leverage Top-Down Bottom-Up (TDBU) floorplan methodology to create and refine the RFID or Reader IC floorplan - collaborating with circuit and block-level layout designers on sizing, pin rings, inter ...
Cadence Allegro Package Designer / APD+ / SiP, Siemens Xpedition Package Designer, Synopsys IC ... Familiarity with mask and RDL vendor flows, GDS-based layout environments (Virtuoso, KLayout), and ...
Cadence Allegro Package Designer / APD+ / SiP, Siemens Xpedition Package Designer, Synopsys IC ... Familiarity with mask and RDL vendor flows, GDS-based layout environments (Virtuoso, KLayout), and ...
Senior Staff Design Engineer, IC Layout
$158K - $238K/yr
Leverage Top-Down Bottom-Up (TDBU) floorplan methodology to create and refine the RFID or Reader IC floorplan - collaborating with circuit and block-level layout designers on sizing, pin rings, inter ...
Senior Staff Design Engineer, IC Layout
$158K - $238K/yr
Leverage Top-Down Bottom-Up (TDBU) floorplan methodology to create and refine the RFID or Reader IC floorplan - collaborating with circuit and block-level layout designers on sizing, pin rings, inter ...
Leverage Top-Down Bottom-Up (TDBU) floorplan methodology to create and refine the RFID or Reader IC floorplan -- collaborating with circuit and block-level layout designers on sizing, pin rings ...
Quick apply
Leverage Top-Down Bottom-Up (TDBU) floorplan methodology to create and refine the RFID or Reader IC floorplan -- collaborating with circuit and block-level layout designers on sizing, pin rings ...
Cadence Allegro Package Designer / APD+ / SiP, Siemens Xpedition Package Designer, Synopsys IC ... Familiarity with mask and RDL vendor flows, GDS-based layout environments (Virtuoso, KLayout), and ...
Cadence Allegro Package Designer / APD+ / SiP, Siemens Xpedition Package Designer, Synopsys IC ... Familiarity with mask and RDL vendor flows, GDS-based layout environments (Virtuoso, KLayout), and ...
Mixed Signal IC Layout Design Engineer - Contractor
North, SC · On-site
$100K - $500K/yr
Partner closely with circuit designers to plan and implement fullcustom analog/mixedsignal layouts for blocks such as PLLs, VCOs, ADCs, DACs, LDOs, bandgaps, comparators, clock generators, and ...
Mixed Signal IC Layout Design Engineer - Contractor
North, SC · On-site
$100K - $500K/yr
Partner closely with circuit designers to plan and implement fullcustom analog/mixedsignal layouts for blocks such as PLLs, VCOs, ADCs, DACs, LDOs, bandgaps, comparators, clock generators, and ...
Senior Design Evaluation Engineer
Durham, NC · On-site
$90 - $120/hr
Our team of IC designers, mask designers, and design evaluation engineers work in various sites across the globe with a growing concentration in the Research Triangle. In addition to power ...
Senior Design Evaluation Engineer
Durham, NC · On-site
$90 - $120/hr
Our team of IC designers, mask designers, and design evaluation engineers work in various sites across the globe with a growing concentration in the Research Triangle. In addition to power ...
Senior Design Evaluation Engineer
Durham, NC · On-site
$100K - $135K/yr
Our team of IC designers, mask designers, and design evaluation engineers work in various sites across the globe with a growing concentration in the Research Triangle. In addition to power ...
Senior Design Evaluation Engineer
Durham, NC · On-site
$100K - $135K/yr
Our team of IC designers, mask designers, and design evaluation engineers work in various sites across the globe with a growing concentration in the Research Triangle. In addition to power ...
Senior Design Evaluation Engineer
$101K - $138K/yr
Our team of IC designers, mask designers, and design evaluation engineers work in various sites across the globe with a growing concentration in the Research Triangle. In addition to power ...
Senior Design Evaluation Engineer
$101K - $138K/yr
Our team of IC designers, mask designers, and design evaluation engineers work in various sites across the globe with a growing concentration in the Research Triangle. In addition to power ...
Analog Circuit Design Engineer
Cupertino, CA · On-site
$249K/yr
We have an opportunity for a visionary and uncommonly talented IC Designer. As a member of our ... Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ...
Analog Circuit Design Engineer
Cupertino, CA · On-site
$249K/yr
We have an opportunity for a visionary and uncommonly talented IC Designer. As a member of our ... Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ...
Supervise closely IC circuit/mask designers, provide floorplan and layout guidelines * Support lab characterization of silicon * Tackle challenges of circuit design in deep submicron CMOS * Take ...
Supervise closely IC circuit/mask designers, provide floorplan and layout guidelines * Support lab characterization of silicon * Tackle challenges of circuit design in deep submicron CMOS * Take ...
Supervise closely IC circuit/mask designers, provide floorplan and layout guidelines * Support lab characterization of silicon * Tackle challenges of circuit design in deep submicron CMOS * Take ...
Supervise closely IC circuit/mask designers, provide floorplan and layout guidelines * Support lab characterization of silicon * Tackle challenges of circuit design in deep submicron CMOS * Take ...
Supervise closely IC circuit/mask designers, provide floorplan and layout guidelines * Support lab characterization of silicon * Tackle challenges of circuit design in deep submicron CMOS * Take ...
Supervise closely IC circuit/mask designers, provide floorplan and layout guidelines * Support lab characterization of silicon * Tackle challenges of circuit design in deep submicron CMOS * Take ...
Supervise closely IC circuit/mask designers, provide floorplan and layout guidelines * Support lab characterization of silicon * Tackle challenges of circuit design in deep submicron CMOS * Take ...
Supervise closely IC circuit/mask designers, provide floorplan and layout guidelines * Support lab characterization of silicon * Tackle challenges of circuit design in deep submicron CMOS * Take ...
Senior EDA/CAD Engineer
Palo Alto, CA · On-site
$123K - $169K/yr
Own and maintain the custom design environment used by custom schematic and mask designers. * Support and maintain CAD tools used by IC designers including: * Virtuoso ADE, ADS various simulation ...
Senior EDA/CAD Engineer
Palo Alto, CA · On-site
$123K - $169K/yr
Own and maintain the custom design environment used by custom schematic and mask designers. * Support and maintain CAD tools used by IC designers including: * Virtuoso ADE, ADS various simulation ...
RF/Analog/Mixed Signal IC Design Engineer
$175K - $308K/yr
... an RF IC design engineer, you will be responsible for providing RF solutions for cellular ... Working closely with the mask design team to implement layout views of designs. Preferred ...
RF/Analog/Mixed Signal IC Design Engineer
$175K - $308K/yr
... an RF IC design engineer, you will be responsible for providing RF solutions for cellular ... Working closely with the mask design team to implement layout views of designs. Preferred ...
RF/Analog/Mixed Signal IC Design Engineer
$175K - $308K/yr
... an RF IC design engineer, you will be responsible for providing RF solutions for cellular ... Working closely with the mask design team to implement layout views of designs. Preferred ...
RF/Analog/Mixed Signal IC Design Engineer
$175K - $308K/yr
... an RF IC design engineer, you will be responsible for providing RF solutions for cellular ... Working closely with the mask design team to implement layout views of designs. Preferred ...
Senior EDA/CAD Engineer
Palo Alto, CA · On-site
$122K - $168K/yr
Own and maintain the custom design environment used by custom schematic and mask designers. * Support and maintain CAD tools used by IC designers including: * Virtuoso ADE, ADS various simulation ...
Senior EDA/CAD Engineer
Palo Alto, CA · On-site
$122K - $168K/yr
Own and maintain the custom design environment used by custom schematic and mask designers. * Support and maintain CAD tools used by IC designers including: * Virtuoso ADE, ADS various simulation ...
Senior EDA/CAD Engineer
Palo Alto, CA · On-site
$122K - $168K/yr
Own and maintain the custom design environment used by custom schematic and mask designers. * Support and maintain CAD tools used by IC designers including: * Virtuoso ADE, ADS various simulation ...
Senior EDA/CAD Engineer
Palo Alto, CA · On-site
$122K - $168K/yr
Own and maintain the custom design environment used by custom schematic and mask designers. * Support and maintain CAD tools used by IC designers including: * Virtuoso ADE, ADS various simulation ...
Ic Mask Designer information
See salary details
$150K - $154.3K
9% of jobs
$154.3K - $158.5K
9% of jobs
$162.1K is the 25th percentile. Wages below this are outliers.
$158.5K - $162.8K
10% of jobs
$162.8K - $167.1K
10% of jobs
$167.1K - $171.4K
9% of jobs
The median wage is $173.7K / yr.
$171.4K - $175.6K
10% of jobs
$175.6K - $179.9K
9% of jobs
$179.9K - $184.2K
10% of jobs
$185.4K is the 75th percentile. Wages above this are outliers.
$184.2K - $188.5K
10% of jobs
$188.5K - $192.7K
9% of jobs
$192.7K - $197K
10% of jobs
$150K
$175K
$197K
How much do ic mask designer jobs pay per year?
What is an IC mask designer?
What are some common challenges IC mask designers face when collaborating with circuit design and layout teams?
What are the key skills and qualifications needed to thrive as an IC mask designer, and why are they important?
What is the difference between Ic Mask Designer vs IC Process Engineer?
| Aspect | IC Mask Designer | IC Process Engineer |
|---|---|---|
| Required Credentials | Typically a degree in Electrical Engineering, Microelectronics, or related field; familiarity with CAD tools | Degree in Chemical, Electrical, or Materials Engineering; knowledge of fabrication processes |
| Work Environment | Design labs, cleanrooms, CAD software environments | Manufacturing facilities, cleanrooms, process development labs |
| Industry Usage | Designing photomasks for semiconductor fabrication | Developing and optimizing semiconductor manufacturing processes |
| Common Search/Comparison | IC Mask Designer vs IC Process Engineer |
The IC Mask Designer focuses on creating detailed photomask layouts used in semiconductor fabrication, requiring expertise in CAD tools and design principles. In contrast, the IC Process Engineer works on developing and refining manufacturing processes to produce semiconductors efficiently. Both roles are essential in the semiconductor industry but differ in their focus—design versus process development.
What states have the most Ic Mask Designer jobs?
States with the most job openings for Ic Mask Designer jobs include:
What job categories do people searching Ic Mask Designer jobs look for?
The top searched job categories for Ic Mask Designer jobs are:

Full-time
Posted 27 days ago
Analog Devices rating
8.5
Based on 17 frontline employees who took The Breakroom Quiz
33rd of 157 rated electronics manufacturers
Job description
ADI fosters a culture that focuses on employees through beneficial programs, aligned goals, continuous learning opportunities, and practices that create a more sustainable future.
About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.
Job Description:
The Automotive Solutions Group needs entry level computer draftsman interested in learning mask design for advanced analog and mixed-signal ICs. You will work as a team with layout designers and engineers, local and/or globally to complete full chip projects.
Responsibilities include all aspects of IC mask design from creating full chip floor plans, planning schedules, hookup, and verification to tape out. On the job training provided to develop your skills.
Minimum Qualifications:
- Comfortable with computers and working on a computer continuously as a full-time job.
- Good written and verbal communication skills
- Good puzzle solving skills
- Good spatial awareness skills
- Eager to learn with strong memory retention skills
- Ability to work well in a team environment
- Accepting of change that comes from innovation
- Detail-oriented
Preferred Qualifications:
- High school graduate or equivalent (General Education Diploma).
- At least eighteen years old.
- Computer programming / coding a plus
Key learning objectives of the program:
- Use Cadence Virtuoso Layout XL editor
- Generate high-quality placements.
- Carefully and methodically route sub-cells and blocks.
- Basic Power Fet metallization.
- LVS, DRC, Latchup and Antenna Verification using Calibre
- Gain ability to work on layouts independently.
- Basic proficiency using Linux
What are the key competencies required to be successful on the program?
- Comfortable with computers and working on a computer continuously as a full-time job.
- Good written and verbal communication skills
- Good puzzle solving skills
- Good spatial awareness skills
- Eager to learn with strong memory retention skills
- Ability to work well in a team environment
- Ability to embrace change
- Detail-oriented
- Schedule meetings with SLD's to ask questions and gain knowledge
- Spend time studying things you need to understand
Length of the program
6-month training period with a purpose of progressing in the Layout Career Path.
What training will be provided?
A class-style setting and seating arrangement with assignments and exams to show retention of learning. Multiple mentors to help give a well-rounded learning experience. Exams will not test beyond what has been taught.
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
EEO is the Law: Notice of Applicant Rights Under the Law.
Job Req Type: Graduate Job
Required Travel: No
What Analog Devices employees say
Pay
Benefits
Hours and flexibility
Workplace
Get the full story on Breakroom
About Analog Devices
Sourced by ZipRecruiter
Analog Devices (NASDAQ: ADI) designs and manufactures semiconductor products and solutions. We enable our customers to interpret the world around us by intelligently bridging the physical and digital worlds with unmatched technologies that sense, measure and connect.
Industry
Electrical equipment, appliance, and component manufacturing
Company size
5,001 - 10,000 Employees
Headquarters location
Norwood, MA, US
Year founded
1965