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Ic Layout Jobs in California (NOW HIRING)

Saige Partners

ANalog Layout Engineer

San Jose, CA · On-site

$236K/yr

Senior High-Speed Mixed-Signal / Analog IC Layout Engineer (San Jose, CA)As an Analog Layout Engineer, you will be responsible for: Layout of Analog / High Speed transceiver circuit blocks such as ...

Glow Networks

Analog Layout Engineer

Santa Clara, CA · On-site

$237K/yr

Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 5nm, 7nm, 16nm, 28nm, 40nm and 65nm following best ...

SpaceX

RFIC Layout Designer (RFIC Engineering)

Irvine, CA · On-site

$120K - $170K/yr

You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and ...

Qorvo, Inc.

Staff Layout Design Engineer

Sacramento, CA · On-site

$144K - $187K/yr

Associates Degree in Electronic/IC layout CAD specialization or related program and 10+ years of IC layout experience * Ability to layout analog circuitry in a size/time constrained environment

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How much do ic layout jobs pay per hour?

As of Aug 14, 2026, the average hourly pay for ic layout in California is $21.54, according to ZipRecruiter salary data. Most workers in this role earn between $15.43 and $21.83 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive in the IC layout position, and why are they important?

To thrive as an IC Layout professional, you need strong proficiency in analog and digital integrated circuit (IC) layout design, a solid understanding of semiconductor physics, and a degree in electrical engineering or a related field. Expertise with Electronic Design Automation (EDA) tools such as Cadence Virtuoso, Mentor Graphics, or Synopsys is typically required. Attention to detail, effective communication, and the ability to collaborate with circuit design engineers are valuable soft skills. These qualities ensure that layouts are precise, manufacturable, and meet stringent performance and reliability standards in the semiconductor industry.

What are some common challenges faced by IC layout engineers, and how do they typically overcome them?

IC Layout engineers often encounter challenges such as balancing area constraints with performance requirements, minimizing parasitic effects, and ensuring adherence to complex design rules. These challenges are addressed by leveraging advanced EDA tools, closely collaborating with circuit designers to understand specific needs, and frequently reviewing and updating the layout to align with fabrication requirements. Strong analytical thinking and attention to detail are essential for identifying and solving these issues. By keeping up with evolving technology and continually honing their skills, IC Layout engineers can efficiently deliver robust and high-quality designs.

What is an IC layout?

An IC Layout job involves designing the physical layout of integrated circuits (ICs) to ensure they meet electrical, manufacturing, and performance requirements. Layout engineers use specialized software to place and route transistors, resistors, and metal interconnects while following design rules and constraints. They work closely with circuit designers to optimize the layout for power, performance, and area. The role requires knowledge of semiconductor manufacturing processes and layout verification techniques such as DRC (Design Rule Checking) and LVS (Layout vs. Schematic).

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Ic Layout jobs near you
Infographic showing various Ic Layout job openings in California as of July 2026, with employment types broken down into 89% Full Time, and 11% Contract. Highlights an 89% In-person, and 11% Remote job distribution, with an average salary of $44,808 per year, or $21.5 per hour.

Analog IC Layout Engineer

Neuralink

South San Francisco, CA

Full-time

Re-posted 17 days ago

Job description

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description and Responsibilities:

We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer, your responsibilities will include:

  • Crafting state-of-the-art layouts for mixed-signal and analog circuits
    • Amplifiers
    • Filters
    • Switched capacitor circuits
    • Oscillators
    • Data converters
    • Power management circuits
  • Reviewing layout floorplans and analyzing high-fidelity circuits with circuit engineers
  • Physical verification of custom IC mask layouts (LVS, DRC, ERC)

Required Qualifications:

  • Bachelor of Science in Computer Engineering or related field
  • 2+ years of experience in analog and mixed-signal IC layout design
  • 1+ year experience with FinFET technologies
  • Ability to identify the best approach to solving problems

Preferred Qualifications:

  • Programming/scripting knowledge in SKILL, TCL, Shell, C/C++, and/or Python
  • Proven expertise in implementing analog and mixed-signal layout designs, achieving tight matching, low noise, and low power consumption
  • Understanding on failure-prone circuit and layout structures
  • Experience with analog DFM standards
  • Experience with layout P-cell design and implementation
  • Experience with layout automation 

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