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Ic Layout Jobs (NOW HIRING)

Samtec

Integrated Circuits (IC) Engineer

Phoenix, AZ · On-site

IC development tasks include the architecture definition, circuit design, synthesis, physical layout, verification, packaging and testing of hardware prototypes and high-volume IC products. Essential ...

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How much do ic layout jobs pay per hour?

As of Jun 1, 2026, the average hourly pay for ic layout in the United States is $21.83, according to ZipRecruiter salary data. Most workers in this role earn between $15.62 and $22.12 per hour, depending on experience, location, and employer.

What is an IC Layout job?

An IC Layout job involves designing the physical layout of integrated circuits (ICs) to ensure they meet electrical, manufacturing, and performance requirements. Layout engineers use specialized software to place and route transistors, resistors, and metal interconnects while following design rules and constraints. They work closely with circuit designers to optimize the layout for power, performance, and area. The role requires knowledge of semiconductor manufacturing processes and layout verification techniques such as DRC (Design Rule Checking) and LVS (Layout vs. Schematic).

What are the key skills and qualifications needed to thrive in the Ic Layout position, and why are they important?

To thrive as an IC Layout professional, you need strong proficiency in analog and digital integrated circuit (IC) layout design, a solid understanding of semiconductor physics, and a degree in electrical engineering or a related field. Expertise with Electronic Design Automation (EDA) tools such as Cadence Virtuoso, Mentor Graphics, or Synopsys is typically required. Attention to detail, effective communication, and the ability to collaborate with circuit design engineers are valuable soft skills. These qualities ensure that layouts are precise, manufacturable, and meet stringent performance and reliability standards in the semiconductor industry.

What are some common challenges faced by IC Layout engineers, and how do they typically overcome them?

IC Layout engineers often encounter challenges such as balancing area constraints with performance requirements, minimizing parasitic effects, and ensuring adherence to complex design rules. These challenges are addressed by leveraging advanced EDA tools, closely collaborating with circuit designers to understand specific needs, and frequently reviewing and updating the layout to align with fabrication requirements. Strong analytical thinking and attention to detail are essential for identifying and solving these issues. By keeping up with evolving technology and continually honing their skills, IC Layout engineers can efficiently deliver robust and high-quality designs.
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Ic Layout jobs near you
Sr IC Layout Designer ( Sunnyvale CA - Onsite)

Sr IC Layout Designer ( Sunnyvale CA - Onsite)

Encore Semi, Inc.

Sunnyvale, CA • On-site

$130K - $160K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Posted 9 days ago

Job description

POSITION DETAILS:
You will be part of the Encore Semi design and circuit layout team, creating next generation products for commercial, civil and space missions. You will work as part of a team with the RFIC/Mixed Signal Designers and Layout Designers on chip layout and custom analog and RFIC IP blocks in technologies down to 3 nm.
Location:  100% on-site in Redmond WA
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: Must be US citizen or Lawful Permanent Resident.
Responsibilities:
Working with IC designers and chip leads to determine the chip and block floorplan, including strategies for power and ground distribution.
Performing layout of custom RF and analog circuit blocks with attention to matching and minimizing parasitics in the layout.
Accurately estimating the schedule for the layout work and identifying areas of complexity that needs early investigation.
Performing DRC, ERC and LVS checks and resolving errors.
Key Qualifications:
  • Strong analog layout skills.
  • Expert-level knowledge with Cadence Virtuoso tool suite.
  • Expert-level knowledge with Mentor Graphics Calibre.
  • Strong experience in advanced node IC layout, must have experience in 7 nm (FinFET) or below.
  • The ideal candidate has experience with TSMC 3/4/5nm technology. 
  • Experience with layout of analog blocks ADC / DAC / PLLs.  
  • Experience with 112G SerDes layout a plus.
  • Understand layout considerations for device matching, coupling and noise isolation.
The anticipated annual base salary for this position is between $130,000 to $160,000, which also includes a comprehensive benefits package.
Full-Time Benefits:
• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
• Dental & Vision: Company covers 50% of premiums for Employee and Dependents
• Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
• Employee Assistant Program (EAP)
• 401k - Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.