Tucson, AZ · On-site
$116K - $160K/yr
We have a PERM position in sunny Tucson, AZ for an ASIC FPGA Designer. There are several positions ... Engineer (ASIC Design) FPGA ASIC design experience required. Knowledge and experience including ...
Tucson, AZ · On-site
$116K - $160K/yr
We have a PERM position in sunny Tucson, AZ for an ASIC FPGA Designer. There are several positions ... Engineer (ASIC Design) FPGA ASIC design experience required. Knowledge and experience including ...
Tucson, AZ · On-site
$114K - $157K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Tucson, AZ · On-site
$114K - $157K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Chandler, AZ · On-site
$133K/yr
Staff AI/ML Digital Design Engineer Locations: Chandler, AZ; Spain; France About Analog Devices ... Lead RTL digital design for complex blocks and subsystems with AI/MLassisted methodologies * Apply ...
Chandler, AZ · On-site
$133K/yr
Staff AI/ML Digital Design Engineer Locations: Chandler, AZ; Spain; France About Analog Devices ... Lead RTL digital design for complex blocks and subsystems with AI/MLassisted methodologies * Apply ...
Chandler, AZ · On-site
$133K/yr
Lead RTL digital design for complex blocks and subsystems with AI/ML-assisted methodologies * Apply AI/ML techniques to enhance digital design workflows such as synthesis, timing closure, and ...
Chandler, AZ · On-site
$133K/yr
Lead RTL digital design for complex blocks and subsystems with AI/ML-assisted methodologies * Apply AI/ML techniques to enhance digital design workflows such as synthesis, timing closure, and ...
Support and deliver ASIC/Digital tool/flow/methodologysolutions using Cadence tool suites to ... Drive quality improvements in design kits and documentation through ASIC design reference flow ...
Support and deliver ASIC/Digital tool/flow/methodologysolutions using Cadence tool suites to ... Drive quality improvements in design kits and documentation through ASIC design reference flow ...
Support and deliver ASIC/Digital tool/flow/methodology solutions using Cadence tool suites to ... Drive quality improvements in design kits and documentation through ASIC design reference flow ...
Support and deliver ASIC/Digital tool/flow/methodology solutions using Cadence tool suites to ... Drive quality improvements in design kits and documentation through ASIC design reference flow ...
Scottsdale, AZ · On-site
$135K - $150K/yr
Strong proficiency in VHDL and/or Verilog/SystemVerilog for synthesizable RTL design * Hands-on ... General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions ...
Scottsdale, AZ · On-site
$135K - $150K/yr
Strong proficiency in VHDL and/or Verilog/SystemVerilog for synthesizable RTL design * Hands-on ... General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions ...
Scottsdale, AZ · On-site
$135K - $150K/yr
Strong proficiency in VHDL and/or Verilog/SystemVerilog for synthesizable RTL design * Hands-on ... Company Overview General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high ...
Scottsdale, AZ · On-site
$135K - $150K/yr
Strong proficiency in VHDL and/or Verilog/SystemVerilog for synthesizable RTL design * Hands-on ... Company Overview General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high ...
Chandler, AZ · On-site
$183K - $274K/yr
This role will be for a design engineer for the ASIC on the logic board for the Sentinel ISD. The engineer will update the existing design for new or modified requirements from the Sentinel program.
Chandler, AZ · On-site
$183K - $274K/yr
This role will be for a design engineer for the ASIC on the logic board for the Sentinel ISD. The engineer will update the existing design for new or modified requirements from the Sentinel program.
Contribute to the full IC development lifecycle, including RTL design, synthesis, place and route ... Engineer your future. We empower our employees to truly own their career and development. Come ...
Contribute to the full IC development lifecycle, including RTL design, synthesis, place and route ... Engineer your future. We empower our employees to truly own their career and development. Come ...
Tucson, AZ · On-site
$116K - $142K/yr
We are seeking a highly motivated and versatile engineer to join our dynamic Current Sensing ... Contribute to the full IC development lifecycle, including RTL design, synthesis, place and route ...
Tucson, AZ · On-site
$116K - $142K/yr
We are seeking a highly motivated and versatile engineer to join our dynamic Current Sensing ... Contribute to the full IC development lifecycle, including RTL design, synthesis, place and route ...
Tucson, AZ · On-site
$116K - $142K/yr
Contribute to the full IC development lifecycle, including RTL design, synthesis, place and route ... Engineer your future. We empower our employees to truly own their career and development. Come ...
Tucson, AZ · On-site
$116K - $142K/yr
Contribute to the full IC development lifecycle, including RTL design, synthesis, place and route ... Engineer your future. We empower our employees to truly own their career and development. Come ...
As a Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
As a Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
As a Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
As a Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
As a Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
As a Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$116K - $160K/yr
As a Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$116K - $160K/yr
As a Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$114K - $157K/yr
As a Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$114K - $157K/yr
As a Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
$114K - $157K/yr
... • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification (SystemVerilog coding with UVM) • Xilinx or Microsemi devices and flow tools • Delivering FPGA/ASIC solutions to system level ...
$114K - $157K/yr
... • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification (SystemVerilog coding with UVM) • Xilinx or Microsemi devices and flow tools • Delivering FPGA/ASIC solutions to system level ...
Tucson, AZ · On-site
$116K/yr
Your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification ... As a design engineer, you will prepare test methods and specifications, assist in preparation of ...
Tucson, AZ · On-site
$116K/yr
Your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification ... As a design engineer, you will prepare test methods and specifications, assist in preparation of ...
$114K - $157K/yr
... • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification (SystemVerilog coding with UVM) • Xilinx or Microsemi devices and flow tools • Delivering FPGA/ASIC solutions to system level ...
$114K - $157K/yr
... • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification (SystemVerilog coding with UVM) • Xilinx or Microsemi devices and flow tools • Delivering FPGA/ASIC solutions to system level ...
| Aspect | Contractual Asic Rtl Design Engineer | Digital IC Design Engineer |
|---|---|---|
| Credentials | Bachelor's/Master's in Electrical Engineering or Computer Engineering | Bachelor's/Master's in Electrical Engineering or Computer Engineering |
| Work Environment | Contract-based, project-specific, often in semiconductor or tech companies | Full-time or contract, working on digital integrated circuit design |
| Industry Usage | Common in semiconductor, electronics, and tech firms for ASIC development | Used across semiconductor, consumer electronics, and communication industries |
Both roles require similar educational backgrounds and work in related environments, focusing on digital circuit design. The main difference is that Contractual Asic Rtl Design Engineers typically work on specific ASIC projects on a contractual basis, while Digital IC Design Engineers may have broader responsibilities in digital chip development, often in full-time roles.
$116K - $160K/yr
Full-time
Posted 7 days ago
