Sr. Logic Design Engineer
$141K - $200K/yr
Responsibilities will include but not limited to: - Develops the logic design, register transfer level (RTL) coding, and simulation for IP block. - Participates in the definition of architecture and ...
Sr. Logic Design Engineer
$141K - $200K/yr
Responsibilities will include but not limited to: - Develops the logic design, register transfer level (RTL) coding, and simulation for IP block. - Participates in the definition of architecture and ...
CPU RTL Design Engineer
$141K - $269K/yr
As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL ...
CPU RTL Design Engineer
$141K - $269K/yr
As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL ...
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high ... Implement specifications/designs in RTL and coordinate the work of other junior designers to ...
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high ... Implement specifications/designs in RTL and coordinate the work of other junior designers to ...
RTL Design Engineer
Phoenix, AZ · On-site
$105K - $200K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip ...
RTL Design Engineer
Phoenix, AZ · On-site
$105K - $200K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip ...
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high ... Implement specifications/designs in RTL and coordinate the work of other junior designers to ...
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high ... Implement specifications/designs in RTL and coordinate the work of other junior designers to ...
As a Physical Design Intern, you will join a highly experienced team. Your key responsibilities ... Pursuing Master's degree (MSEE) with majority of courses relevant to Digital Design, RTL, Digital ...
As a Physical Design Intern, you will join a highly experienced team. Your key responsibilities ... Pursuing Master's degree (MSEE) with majority of courses relevant to Digital Design, RTL, Digital ...
As a Physical Design Intern, you will join a highly experienced team. Your key responsibilities ... Pursuing Master's degree (MSEE) with majority of courses relevant to Digital Design, RTL, Digital ...
As a Physical Design Intern, you will join a highly experienced team. Your key responsibilities ... Pursuing Master's degree (MSEE) with majority of courses relevant to Digital Design, RTL, Digital ...
Senior Synthesis & Place & Route (P&R) Engineer - MRAM Subsystems
Arizona City, AZ · On-site
$120 - $180/hr
You will bridge the gap between RTL logic design, high-density MRAM macro integration, and foundry physical implementation playing a vital role in balancing Power, Performance, Area (PPA), and ...
New
Senior Synthesis & Place & Route (P&R) Engineer - MRAM Subsystems
Arizona City, AZ · On-site
$120 - $180/hr
You will bridge the gap between RTL logic design, high-density MRAM macro integration, and foundry physical implementation playing a vital role in balancing Power, Performance, Area (PPA), and ...
New
FPGA Design Engineer
Tucson, AZ · On-site
$116K - $160K/yr
Develop RTL and support simulation, synthesis, place and route, timing closure, hardware ... Strong understanding of digital logic design, hardware architecture, and hardware/software ...
FPGA Design Engineer
Tucson, AZ · On-site
$116K - $160K/yr
Develop RTL and support simulation, synthesis, place and route, timing closure, hardware ... Strong understanding of digital logic design, hardware architecture, and hardware/software ...
Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design and verify DSP, control, and data-path logic, including calibration and monitoring state machines.
Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design and verify DSP, control, and data-path logic, including calibration and monitoring state machines.
Staff Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design and verify DSP, control, and data-path logic, including calibration and monitoring state machines.
Staff Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design and verify DSP, control, and data-path logic, including calibration and monitoring state machines.
Senior Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design and verify DSP, control, and data-path logic, including calibration and monitoring state machines.
Senior Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design and verify DSP, control, and data-path logic, including calibration and monitoring state machines.
Senior Staff Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design and verify DSP, control, and data-path logic, including calibration and monitoring state machines.
Senior Staff Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
Develop RTL designs using Verilog and support integration into larger SoC environments. * Design and verify DSP, control, and data-path logic, including calibration and monitoring state machines.
Digital IC Design Engineer | DCC DAC
Tucson, AZ · On-site
$116K/yr
Your responsibilities will include defining, RTL coding, simulation, synthesis, timing closure ... A thorough understanding of digital logic design * Familiarity with the SystemVerilog language and ...
Digital IC Design Engineer | DCC DAC
Tucson, AZ · On-site
$116K/yr
Your responsibilities will include defining, RTL coding, simulation, synthesis, timing closure ... A thorough understanding of digital logic design * Familiarity with the SystemVerilog language and ...
Digital and Mixed Signal IC Design/DV Engineer
Tucson, AZ · On-site
$116K/yr
Contribute to the full IC development lifecycle, including RTL design, synthesis, place and route ... A thorough understanding of digital logic design * Familiarity with the Verilog, System Verilog ...
Digital and Mixed Signal IC Design/DV Engineer
Tucson, AZ · On-site
$116K/yr
Contribute to the full IC development lifecycle, including RTL design, synthesis, place and route ... A thorough understanding of digital logic design * Familiarity with the Verilog, System Verilog ...
Digital and Mixed Signal IC Design/DV Engineer
Tucson, AZ · On-site
$116K/yr
Contribute to the full IC development lifecycle, including RTL design, synthesis, place and route ... A thorough understanding of digital logic design * Familiarity with the Verilog, System Verilog ...
Digital and Mixed Signal IC Design/DV Engineer
Tucson, AZ · On-site
$116K/yr
Contribute to the full IC development lifecycle, including RTL design, synthesis, place and route ... A thorough understanding of digital logic design * Familiarity with the Verilog, System Verilog ...
Digital IC Design Engineer | DCC DAC
Tucson, AZ · On-site
$116K/yr
Your responsibilities will include defining, RTL coding, simulation, synthesis, timing closure ... A thorough understanding of digital logic design * Familiarity with the SystemVerilog language and ...
Digital IC Design Engineer | DCC DAC
Tucson, AZ · On-site
$116K/yr
Your responsibilities will include defining, RTL coding, simulation, synthesis, timing closure ... A thorough understanding of digital logic design * Familiarity with the SystemVerilog language and ...
Collaborates with architects, design, verification, and validation engineers during the execution ... Strong background in microarchitecture/RTL/logic development. * Proven ability to resolve complex ...
Collaborates with architects, design, verification, and validation engineers during the execution ... Strong background in microarchitecture/RTL/logic development. * Proven ability to resolve complex ...
Staff Engineer, Design Verification Engineering
Chandler, AZ · On-site
$172K - $199K/yr
Define and verify interfaces, state machines, and controlling logic required to implement new ... RTL and function verification. Alternatively, employer will accept a Bachelor's degree in ...
Staff Engineer, Design Verification Engineering
Chandler, AZ · On-site
$172K - $199K/yr
Define and verify interfaces, state machines, and controlling logic required to implement new ... RTL and function verification. Alternatively, employer will accept a Bachelor's degree in ...
Complete FPGA logic design, coding, simulation, and testing. * Support hardware and software ... Experience in both creating IP from scratch in RTL, and integrating existing IP into RTL and block ...
Complete FPGA logic design, coding, simulation, and testing. * Support hardware and software ... Experience in both creating IP from scratch in RTL, and integrating existing IP into RTL and block ...
Rtl Logic Design Intern information
What is an RTL Logic Design intern?
RTL Logic Design Interns are students or recent graduates who assist in designing, implementing, and verifying digital circuits at the Register Transfer Level (RTL) using hardware description languages like Verilog or VHDL. Their work involves translating high-level functional specifications into efficient digital logic and working closely with senior engineers to create and test modules for chips or FPGAs. Interns gain hands-on experience with tools and methodologies used in the semiconductor industry, such as simulation, synthesis, and debugging. This role is ideal for those pursuing careers in digital hardware design or computer engineering.
What types of projects and tasks can an RTL Logic Design intern expect to work on during their internship?
As an RTL Logic Design Intern, you can expect to work on a variety of tasks such as writing and verifying Register Transfer Level (RTL) code using hardware description languages like Verilog or VHDL. You may assist in developing modules for digital circuits, running simulations, and debugging logic issues. Interns often collaborate closely with senior engineers, gaining exposure to the design flow, synthesis, and timing analysis. This hands-on experience provides a solid foundation in digital design and offers insight into how large-scale integrated circuits are developed in a professional environment.
What are the key skills and qualifications needed to thrive as an RTL Logic Design intern, and why are they important?
To thrive as an RTL Logic Design Intern, you need a solid understanding of digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with simulation tools such as ModelSim, synthesis tools like Synopsys Design Compiler, and version control systems is highly beneficial. Attention to detail, strong problem-solving abilities, and effective teamwork are critical soft skills for this role. These skills and qualities enable accurate, efficient design and verification of digital circuits, which are essential for developing reliable hardware products.
What is the difference between Rtl Logic Design Intern vs Digital Design Intern?
| Aspect | Rtl Logic Design Intern | Digital Design Intern |
|---|---|---|
| Required Skills | Verilog/VHDL, digital logic, hardware description languages | Verilog/VHDL, digital logic, FPGA/ASIC design |
| Work Environment | Hardware design teams, semiconductor companies | Hardware and FPGA development teams, electronics firms |
| Industry Usage | ASIC/FPGA chip design, hardware verification | FPGA prototyping, digital circuit development |
Rtl Logic Design Intern focuses specifically on register-transfer level hardware description and logic design, often emphasizing Verilog or VHDL coding for chip development. Digital Design Intern has a broader scope, including FPGA and digital circuit development. Both roles require similar skills but differ slightly in project focus and application areas.
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For Rtl Logic Design Intern jobs in Arizona, the most frequently searched job titles are:
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Cities in Arizona with the most Rtl Logic Design Intern job openings:
$141K - $200K/yr
Full-time
Medical, Retirement, PTO
Posted 29 days ago
Intel rating
8.7
Based on 147 frontline employees who took The Breakroom Quiz
19th of 159 rated electronics manufacturers
Job description
Job Details:Job Description:
Intel's HIPD team is looking for an experienced senior Logic design engineer to join the rapidly growing UCIE PHY IP for Intel's flagship datacenter/server designs.
Responsibilities will include but not limited to:
- Develops the logic design, register transfer level (RTL) coding, and simulation for IP block.
- Participates in the definition of architecture and microarchitecture features of the block being designed.
- Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.
- Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
- Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Behavior skills we are looking for:
- Excellent written and oral presentation skills, and willing to work across multiple organizations and geographies.
- Effective team player with continuous learning mindset.
- Strong analytical and problem-solving skills.
- Be willing to balance multiple tasks.
- Ramp quickly on new and complex IPs in a dynamic environment is critical.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a Bachelor's degree in Electrical or Computer Engineering or a related field and 4+ years' experience OR a Master's degree in Electrical or Computer Engineering or a related field and 2+ years' experience OR a PhD in Electrical or Computer Engineering or a related field and 1+ years' experience.
Relevant Work Experience must be in:
- RTL/Logic design using System Verilog Language
- Experience with Design of Data path, Power-management flow, Arbitration logic, Clock Domain Crossing, State Machines, UPF
- Experience with Front End design tools for Lint, Synthesis.
- Experience with hardware simulation tools and methodologies (VCS/Verdi).
- Familiarity with IP environment and configuration management tools.
Preferred Qualifications:
- UCIE PHY Design and Mixed-Signal Environment.
- Cross Domain Crossing, Voltage Domain Crossings,
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968