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Intern Analog Layout Design Engineer Jobs in Arizona

Analog Engineer

Phoenix, AZ · On-site

$164.47 - $269.10/hr

  • Medical

  • Retirement

  • PTO

Qualifications * Bachelor's degree in Electrical Engineering, Computer Engineering, or related ... Knowledge of SoC analog layout design checks and methodologies. * Preferred: Advanced knowledge of ...

New

Analog Engineer

Phoenix, AZ

$200K/yr

  • Medical

  • Retirement

  • PTO

As an Analog Circuit Design Engineer, you will be at the forefront of designing and developing ... Collaborate with architecture and layout teams to design circuits that maximize functionality ...

Analog Design Engineer

Phoenix, AZ · On-site

$122K - $172K/yr

  • Medical

  • Retirement

  • PTO

As an Analog Design Engineer at Intel, you will play a pivotal role in developing cutting-edge ... with layout engineers to optimize circuit performance. • Participate in design reviews and ...

Analog Design Engineer

Phoenix, AZ

$122K - $172K/yr

  • Medical

  • Retirement

  • PTO

As an Analog Design Engineer at Intel, you will play a pivotal role in developing cutting-edge ... Support layout activities and work closely with layout engineers to optimize circuit performance.

Analog Design Engineer

Chandler, AZ · On-site

$198K/yr

We are seeking a highly motivated Analog Design Engineer to join a collaborative hardware design ... Lead or support layout implementation, post-layout simulation, and performance optimization ...

Senior Analog Design Engineer

Phoenix, AZ · On-site

$200K/yr

  • Medical

  • Retirement

  • PTO

The position also involves providing guidance to layout engineers and mentoring junior analog ... Core analog design principles, including noise, linearity, matching, and stability. * Hands-on ...

Senior Analog Design Engineer

Phoenix, AZ

$200K/yr

  • Medical

  • Retirement

  • PTO

Create and optimize layouts working closely with layout engineers. Perform circuit analysis ... Technical Leadership Lead analog design projects from specification to silicon validation. Mentor ...

Staff Analog Design Engineer

Chandler, AZ · On-site

$198K/yr

We are seeking a highly motivated Analog Design Engineer to join a collaborative hardware design ... Lead or support layout implementation, post-layout simulation, and performance optimization ...

Senior Analog Design Engineer

Chandler, AZ · On-site

$198K/yr

We are seeking a highly motivated Analog Design Engineer to join a collaborative hardware design ... Lead or support layout implementation, post-layout simulation, and performance optimization ...

Senior/Staff Analog IC Design Engineer

Chandler, AZ · On-site

$150 - $200/hr

  • Medical

  • Dental

  • Vision

  • Retirement

Design and develop core analog and mixed-signal circuit blocks, including bandgap references ... Provide layout guidance and collaborate closely with layout engineers to ensure design intent is ...

New

Senior Analog Design Engineer

Phoenix, AZ · On-site

$190.61 - $269.10/hr

  • Medical

  • Retirement

  • PTO

Design and Development • Design and simulate analog and mixed-signal circuits including ... The position also involves providing guidance to layout engineers and mentoring junior analog ...

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Intern Analog Layout Design Engineer information

What is the difference between Intern Analog Layout Design Engineer vs Intern Digital Layout Design Engineer?

AspectIntern Analog Layout Design EngineerIntern Digital Layout Design Engineer
Required SkillsAnalog circuit fundamentals, layout design, SPICE simulationDigital circuit fundamentals, RTL design, layout automation tools
Work EnvironmentDesign teams focused on analog/mixed-signal ICsDesign teams focused on digital ICs and FPGA/ASIC design
Industry UsageSemiconductor companies, chip design firmsSemiconductor companies, FPGA/ASIC vendors

Intern Analog Layout Design Engineers focus on analog/mixed-signal IC layout, requiring knowledge of analog circuits and layout tools. Intern Digital Layout Design Engineers work on digital ICs, emphasizing digital design principles and automation. Both roles are common in semiconductor industries but differ in technical focus and tools used.

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The most popular types of Analog Layout Design Engineer jobs in Arizona are:

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Cities in Arizona with the most Intern Analog Layout Design Engineer job openings:

$164.47 - $269.10/hr

Other

Medical, Retirement, PTO

Posted yesterday

New


Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 159 rated electronics manufacturers


Job description

Join Intel's Advanced Design Foundational IP Organization (AD-FIP) as an Analog Circuit Design Engineer. You will design and develop cutting‑edge analog circuits in advanced process nodes, directly impacting Intel’s foundational IP and product designs across client, server, and networking technologies.

Responsibilities
  • Design, develop, and implement analog circuits and mixed‑signal IPs, including ADCs, DACs, voltage regulators, and high‑speed I/O interfaces.
  • Perform circuit‑level design, simulation, and optimization to meet power, performance, area, timing, and yield requirements.
  • Create and validate floorplans, extract chip parameters, and simulate analog behavior models.
  • Develop test plans for design verification and evaluate test results to meet specification requirements.
  • Collaborate with architecture and layout teams to maximize functionality, robustness, and electrical performance.
  • Conduct tape‑out activities and ensure successful silicon implementation.
  • Analyze and resolve performance and circuit‑related issues during design and post‑silicon validation phases.
  • Serve as a technical interface to process technology, IP engineers, and product teams, influencing future process node development.
Qualifications
  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field and 8+ years of experience in analog and mixed‑signal circuit design; or Master’s degree with 6+ years; or PhD with 4+ years.
  • 3+ years of experience with analog circuit design, simulation, and verification.
  • Proficiency in CMOS technologies and layout understanding for analog circuits.
  • Experience with tape‑out processes for analog mixed‑signal circuits, including ADCs and DACs.
  • Knowledge of SoC analog layout design checks and methodologies.
  • Preferred: Advanced knowledge of high‑speed parallel or serial I/O links, PLLs, bandgap references, inductors, transmission lines, RF or millimeter‑wave circuits.
  • Preferred: Strong understanding of power delivery networks and integrated power regulators.
  • Preferred: Proven ability to collaborate across teams and influence decisions related to process technology and product development.
Benefits
  • You will receive a competitive salary range of $164,470 – $269,100 USD (depending on location).
  • Stock bonuses and comprehensive benefits including health, retirement, and vacation.
  • Hybrid work model allowing on‑site and off‑site work.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sexual orientation, or any other characteristic protected by local law.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968