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Internship Analog Layout Design Engineer Jobs in Arizona

Intel

Analog Engineer

Phoenix, AZ

$200K/yr

Collaborate with architecture and layout teams to design circuits that maximize functionality ... internship experiences and or schoolwork/classes/research. Minimum Qualifications * Bachelor ...

Cirrus Logic

Analog Design Engineer

Chandler, AZ · On-site

$198K/yr

We are seeking a highly motivated Analog Design Engineer to join a collaborative hardware design ... Lead or support layout implementation, post-layout simulation, and performance optimization ...

Intel Corporation

Senior Analog Design Engineer

Phoenix, AZ · On-site

$200K/yr

The position also involves providing guidance to layout engineers and mentoring junior analog ... Core analog design principles, including noise, linearity, matching, and stability. * Hands-on ...

Intel

Senior Analog Design Engineer

Phoenix, AZ

$200K/yr

Create and optimize layouts working closely with layout engineers. Perform circuit analysis ... Technical Leadership Lead analog design projects from specification to silicon validation. Mentor ...

Cirrus Logic

Staff Analog Design Engineer

Chandler, AZ · On-site

$198K/yr

We are seeking a highly motivated Analog Design Engineer to join a collaborative hardware design ... Lead or support layout implementation, post-layout simulation, and performance optimization ...

Cirrus Logic

Senior Analog Design Engineer

Chandler, AZ · On-site

$198K/yr

We are seeking a highly motivated Analog Design Engineer to join a collaborative hardware design ... Lead or support layout implementation, post-layout simulation, and performance optimization ...

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Internship Analog Layout Design Engineer information

What types of projects can an Internship Analog Layout Design Engineer expect to work on, and how is mentorship typically provided in this role?

As an Internship Analog Layout Design Engineer, you will often work on projects involving the physical layout of analog and mixed-signal circuits, such as amplifiers, ADCs, or power management blocks. You can expect to collaborate closely with senior layout engineers and circuit designers, receiving guidance on best practices, design reviews, and tool usage. Mentorship is typically provided through regular check-ins, code reviews, and informal Q&A sessions, allowing you to learn industry-standard CAD tools and layout methodologies while contributing to real silicon tape-outs.

What are the key skills and qualifications needed to thrive as an Internship Analog Layout Design Engineer, and why are they important?

To thrive as an Internship Analog Layout Design Engineer, you need a solid understanding of analog circuit fundamentals, semiconductor device physics, and coursework or experience in microelectronics. Familiarity with EDA tools such as Cadence Virtuoso, and exposure to industry standards like DRC/LVS checks, is typically required. Attention to detail, problem-solving ability, and effective communication are crucial soft skills for this role. These skills and qualifications are essential for creating reliable, efficient circuit layouts that meet technical specifications and support team collaboration in the design process.

What is the difference between Internship Analog Layout Design Engineer vs Analog Layout Design Engineer?

AspectInternship Analog Layout Design EngineerAnalog Layout Design Engineer
QualificationsEnrolled in or recent graduate of Electrical Engineering or related fieldBachelor's or Master's in Electrical Engineering or related field
Work EnvironmentInternship programs, entry-level projects, supervised tasksFull-time professional role, independent project work
ResponsibilitiesAssisting in layout design, learning tools, supporting senior engineersDesigning, optimizing, and verifying analog layouts independently

In summary, an Internship Analog Layout Design Engineer is a temporary, learning-focused role for students or recent graduates, while an Analog Layout Design Engineer is a full-time professional responsible for independent design tasks in the industry.

What does an Internship Analog Layout Design Engineer do?

An Internship Analog Layout Design Engineer assists in the design and layout of analog integrated circuits under the guidance of experienced engineers. Their responsibilities include translating circuit schematics into physical layouts using specialized software, ensuring that the design meets performance and manufacturing requirements. Interns may also run design rule checks (DRC) and layout versus schematic (LVS) verifications to ensure correctness. This role helps interns build skills in analog design, CAD tools, and an understanding of semiconductor manufacturing processes.
What are the most commonly searched types of Analog Layout Design Engineer jobs in Arizona? The most popular types of Analog Layout Design Engineer jobs in Arizona are:
Internship Analog Layout Design Engineer jobs near you
Analog Engineer

Analog Engineer

Intel

Phoenix, AZ

$200K/yr

Full-time

Medical, Retirement, PTO

Posted 11 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 156 rated electronics manufacturers

Job description

Job Details:Job Description: 

The Role and Impact
Join Intel's Advanced Design Foundational IP Organization (AD-FIP) within the Design Technology Platform (DTP), a team that is pivotal in shaping the future of analog and mixed-signal IC design. As an Analog Circuit Design Engineer, you will be at the forefront of designing and developing cutting-edge analog circuits in advanced process nodes. Your work will directly impact Intel's ability to deliver the best-in-class foundational IP and product designs that drive innovation across client, server, and networking technologies. Collaborating with cross-functional teams, you will play a critical role in optimizing performance, power, area, and yield of circuits while pushing the boundaries of what is possible in semiconductor technology.
Key Responsibilities

  • Design, develop, and implement analog circuits and mixed-signal IPs, including ADCs, DACs, voltage regulators, and high-speed I/O interfaces.
  • Perform circuit-level design, simulation, and optimization to meet power, performance, area, timing, and yield requirements.
  • Create and validate floorplans, extract chip parameters, and simulate analog behavior models to ensure robust designs.
  • Develop test plans for design verification and evaluate test results to meet specification requirements.
  • Collaborate with architecture and layout teams to design circuits that maximize functionality, robustness, and electrical capabilities.
  • Conduct tape-out activities for analog and mixed-signal circuits, ensuring successful silicon implementation.
  • Analyze and resolve performance and circuit-related issues during design and post-silicon validation phases.
  • Serve as a technical interface to process technology, IP engineers, and product teams, leveraging design insights to influence future process node development.
Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field and 8+ years of experience in analog and mixed-signal circuit design; or Master's degree with 6+ years of experience; or PhD with 4+ years of experience.

3+ years of experience with the following technical skills

  • Expertise in analog circuit design, simulation, and verification.
  • Proficiency in CMOS technologies and layout understanding for analog circuits.
  • Experience with tape-out processes for analog mixed-signal circuits, including ADCs and DACs.
  • Knowledge of SoC analog layout design checks and methodologies.

Preferred Qualifications

  • Advanced knowledge of high-speed parallel or serial I/O links, clock distribution, or voltage regulator design.
  • Experience with PLLs, bandgap references, inductors, transmission lines, and RF or millimeter-wave circuits.
  • Strong understanding of power delivery networks (PDN) and integrated power regulators.
  • Proven ability to collaborate across teams and influence decisions related to process technology and product development.

Come be a part of Intel's mission to shape the future of technology. Apply today to join a team where innovation, collaboration, and excellence drive the creation of transformative products.

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, AustinBusiness group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

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Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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