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Internship Rfic Design Engineer Jobs in Arizona (NOW HIRING)

Intel

Memory Circuit Design Engineer

Phoenix, AZ · On-site

... Engineering, or a related discipline. Technical Experience: * Design, characterization, and ... PhD with 1-2 years of professional experience gained through either internships or full-time ...

Intel

CPU RTL Design Engineer

Phoenix, AZ · On-site

$141K - $269K/yr

As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic ... internship experiences. Minimum Qualifications: Bachelor's degree in electrical engineering ...

Intel

Silicon Packaging Design Engineer

Phoenix, AZ · On-site

$135K/yr

The Role and Impact As a Silicon Packaging Design Engineer, you will play a critical role in the ... experience, internship experiences and or schoolwork/classes/research. This position is not ...

Alphacore Inc

Analog Design- Internship

Arizona, LA · On-site

Alphacore HQ | Internship Type: Full-time, Paid Alphacore is seeking Analog Design Interns for ... Pursuing BS or MS in Electrical Engineering Coursework in Analog Design and experience with Cadence ...

Intel

Mixed Signal Logic Design Engineer

Phoenix, AZ · On-site

As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high ... internship experiences. * BS degree in Electrical Engineering or Computer Engineering or similar ...

Intel

Mixed Signal Logic Design Engineer

Phoenix, AZ · On-site

As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high ... or internship experiences. Minimum Qualifications: * BS degree in Electrical Engineering or ...

Alphacore Inc

Analog Design- Internship

Tempe, AZ · On-site

Analog Design Intern (Summer & Fall 2026) Location: Alphacore HQ | Internship Type: Full-time, Paid ... engineering team Qualifications: • Pursuing BS or MS in Electrical Engineering • Coursework in ...

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Internship Rfic Design Engineer information

What is the difference between Internship Rfic Design Engineer vs RFIC Design Engineer?

AspectInternship RFIC Design EngineerRFIC Design Engineer
QualificationsEnrolled in or recent graduate of electrical engineering or related fieldBachelor's or master's in electrical engineering, with specialized RFIC knowledge
Work EnvironmentInternship programs, entry-level projects, supervised tasksFull-time professional role, independent project work, team collaboration
ResponsibilitiesAssisting in RFIC design tasks, learning industry tools, supporting senior engineersDesigning, testing, and optimizing RFICs for communication systems

The main difference between an Internship RFIC Design Engineer and an RFIC Design Engineer lies in experience, responsibilities, and career stage. Internships are designed for students or recent graduates gaining industry exposure, while RFIC Design Engineers are experienced professionals responsible for full project execution.

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Internship Rfic Design Engineer jobs near you
Memory Circuit Design Engineer

Memory Circuit Design Engineer

Intel

Phoenix, AZ • On-site

Full-time

Medical, Retirement, PTO

Posted 15 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 145 frontline employees who took The Breakroom Quiz

10th of 141 rated electronics manufacturers

Job description

Job Details:Job Description: 

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.

The Advanced Design (AD) team is part of Intel's larger Design Technology Platform (DTP) Organization and is focused on pathfinding and development of advanced memory technology. These circuits enable best-in-class memory collateral, IP and innovative product design across all generations of Intel process technology. At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable Intel's internal and external customers to get to the market faster with products that include high-performance, high-density, low-power memory at the leading edge of the technology curve and implemented in Intel's advanced CMOS process technologies.

You will be partnering with and leveraging domain experts across various areas of technology development, EDA vendors and product design teams to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on Intel advanced CMOS process technologies. In this position your responsibilities will include, but may not be limited to:

  • Memory pathfinding activities and power, performance and area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement.
  • Memory bit-cell and complex periphery IC layout and automation.
  • Memory array/IP design, memory circuit innovation, test-chip design.
  • Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp.
Qualifications:

You must possess the minimum qualifications listed below to interview for this position. Preferred qualifications are not required but may work to your advantage during the interview process.
Minimum Qualifications:
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline, including 4+ years of professional experience gained through either internships or full-time employment Or a PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline.
Technical Experience:

  • Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM.
  • Design trade-offs between power, performance, and area (PPA).
  • Custom digital circuit design, simulation, layout design, and verification.
  • Knowledge of EDA tools used for custom digital and memory circuit design.

Preferred Qualifications:

  • PhD with 1-2 years of professional experience gained through either internships or full-time employment.
  • Design technology co-optimization (DTCO).
  • Post-Si validation experience.
  • Knowledge of the CMOS ASIC design flow.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, AustinBusiness group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

What Intel employees say

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Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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