Chandler, AZ · On-site
$101K - $136K/yr
Strong digital design engineer with FPGA/ASIC SoC design experience * Strong FPGA Implementation ... Capable of creating RTL simulations to identify and resolve most issues before hardware tests
Quick apply
Chandler, AZ · On-site
$101K - $136K/yr
Strong digital design engineer with FPGA/ASIC SoC design experience * Strong FPGA Implementation ... Capable of creating RTL simulations to identify and resolve most issues before hardware tests
Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint ... Experience with ASIC design flow including LINT, Formal, CDC/RDC, power estimations, MBIST/DFT ...
Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint ... Experience with ASIC design flow including LINT, Formal, CDC/RDC, power estimations, MBIST/DFT ...
Gilbert, AZ · On-site
$98K - $147K/yr
HDL design for FPGA and/or ASIC applications * FPGA/ASIC verification via simulation and emulation ... Experience in RTL design for an aerospace environment or space application * Proficient in FPGA ...
Gilbert, AZ · On-site
$98K - $147K/yr
HDL design for FPGA and/or ASIC applications * FPGA/ASIC verification via simulation and emulation ... Experience in RTL design for an aerospace environment or space application * Proficient in FPGA ...
Gilbert, AZ · On-site
$98K - $147K/yr
HDL design for FPGA and/or ASIC applications * FPGA/ASIC verification via simulation and emulation ... Experience in RTL design for an aerospace environment or space application * Proficient in FPGA ...
Gilbert, AZ · On-site
$98K - $147K/yr
HDL design for FPGA and/or ASIC applications * FPGA/ASIC verification via simulation and emulation ... Experience in RTL design for an aerospace environment or space application * Proficient in FPGA ...
As a Principal Digital Design Engineer, you will lead the architecture and implementation of ... Lead RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and power ...
As a Principal Digital Design Engineer, you will lead the architecture and implementation of ... Lead RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and power ...
As a Staff Digital Design Engineer, you will develop complex digital subsystems within ADI's mixed ... Execute RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and ...
As a Staff Digital Design Engineer, you will develop complex digital subsystems within ADI's mixed ... Execute RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and ...
Tucson, AZ · On-site
$116K/yr
Ownership of RTL design & DV activities including technical ownership as well as schedule planning ... Engineer your future. We empower our employees to truly own their career and development. Come ...
Tucson, AZ · On-site
$116K/yr
Ownership of RTL design & DV activities including technical ownership as well as schedule planning ... Engineer your future. We empower our employees to truly own their career and development. Come ...
As a Staff Digital Design Engineer, you will develop complex digital subsystems within ADI's mixed ... Execute RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and ...
As a Staff Digital Design Engineer, you will develop complex digital subsystems within ADI's mixed ... Execute RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and ...
Implement specifications/designs in RTL and coordinate the work of other junior designers to ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Implement specifications/designs in RTL and coordinate the work of other junior designers to ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Implement specifications/designs in RTL and coordinate the work of other junior designers to ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Implement specifications/designs in RTL and coordinate the work of other junior designers to ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Chandler, AZ · On-site
$133K/yr
Complete high-quality, area-optimal, low-power RTL design using industry-standard hardware ... Collaborate with architects, analog designers, test/product/quality/bench engineers and software ...
Chandler, AZ · On-site
$133K/yr
Complete high-quality, area-optimal, low-power RTL design using industry-standard hardware ... Collaborate with architects, analog designers, test/product/quality/bench engineers and software ...
As a Principal Digital Design Engineer, you will lead the architecture and implementation of ... Lead RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and power ...
As a Principal Digital Design Engineer, you will lead the architecture and implementation of ... Lead RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and power ...
Join Legion Technical Solutions LLC as a Digital Design Engineer 4 in Tucson, AZ, where innovation ... Proficiency in FPGA and ASIC design tools. * Strong understanding of digital signal processing ...
Quick apply
Join Legion Technical Solutions LLC as a Digital Design Engineer 4 in Tucson, AZ, where innovation ... Proficiency in FPGA and ASIC design tools. * Strong understanding of digital signal processing ...
Chandler, AZ · On-site
$133K/yr
Complete high-quality, area-optimal, low-power RTL design using industry-standard hardware ... Collaborate with architects, analog designers, test/product/quality/bench engineers and software ...
Chandler, AZ · On-site
$133K/yr
Complete high-quality, area-optimal, low-power RTL design using industry-standard hardware ... Collaborate with architects, analog designers, test/product/quality/bench engineers and software ...
Phoenix, AZ · On-site
$135K - $139K/yr
... ASIC/SoC design Min. * Qualifications: 0-1 yrs of exp. Enginner - CL11 & CL10 Master's degree in Electrical Eng. or Comp. Science RTL2GDSII exp. on advanced tech. nodes (7nm and below) Exp. w/low ...
Phoenix, AZ · On-site
$135K - $139K/yr
... ASIC/SoC design Min. * Qualifications: 0-1 yrs of exp. Enginner - CL11 & CL10 Master's degree in Electrical Eng. or Comp. Science RTL2GDSII exp. on advanced tech. nodes (7nm and below) Exp. w/low ...
Join Legion Technical Solutions LLC as a Digital Design Engineer in Tucson, AZ, where innovation ... Strong knowledge of FPGA and ASIC design methodologies. * Proficiency in design software such as ...
Quick apply
Join Legion Technical Solutions LLC as a Digital Design Engineer in Tucson, AZ, where innovation ... Strong knowledge of FPGA and ASIC design methodologies. * Proficiency in design software such as ...
Tempe, AZ · On-site
$176K - $264K/yr
As a Design Verification Engineer, you will be part of a verification team responsible for the full cycle of RTL verification for FPGA and ASIC designs. You will be responsible for: * Design ...
Tempe, AZ · On-site
$176K - $264K/yr
As a Design Verification Engineer, you will be part of a verification team responsible for the full cycle of RTL verification for FPGA and ASIC designs. You will be responsible for: * Design ...
Phoenix, AZ · On-site
$122K - $168K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Phoenix, AZ · On-site
$122K - $168K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
$116K - $160K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
$116K - $160K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
$116K - $160K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
$116K - $160K/yr
As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
| Aspect | Contractual Asic Rtl Design Engineer | Digital IC Design Engineer |
|---|---|---|
| Credentials | Bachelor's/Master's in Electrical Engineering or Computer Engineering | Bachelor's/Master's in Electrical Engineering or Computer Engineering |
| Work Environment | Contract-based, project-specific, often in semiconductor or tech companies | Full-time or contract, working on digital integrated circuit design |
| Industry Usage | Common in semiconductor, electronics, and tech firms for ASIC development | Used across semiconductor, consumer electronics, and communication industries |
Both roles require similar educational backgrounds and work in related environments, focusing on digital circuit design. The main difference is that Contractual Asic Rtl Design Engineers typically work on specific ASIC projects on a contractual basis, while Digital IC Design Engineers may have broader responsibilities in digital chip development, often in full-time roles.
$101K - $136K/yr
Full-time
Posted 5 days ago
Job Title: Senior FPGA Engineer III
Department: Engineering->Platforms->FPGA SoC Group
Reports To: Director, Platforms
FLSA Status: Exempt
Last Modified: 9/10/2025
Level: T3
Location Chandler, AZ – Onsite 5 Days a week
Company Overview
Comtech Telecommunications Corp. is a leading global technology company providing terrestrial and wireless network solutions, next-generation 9-1-1 emergency services, satellite and space communications technologies, and cloud-native capabilities to commercial and government customers around the world. Our unique culture of innovation and employee empowerment unleashes a relentless passion for customer success. With multiple facilities located in technology corridors throughout the United States and around the world, Comtech leverages our global presence, technology leadership, and decades of experience to create the world’s most innovative communications solutions. For more information, please visit www.comtech.com.
We’re seeking curious, growth-minded thinkers to help shape our vision, structures, and systems; playing a key role as we launch into our ambitious future. If you’re invigorated by our mission, values, and drive to change the world — we’d love to have you apply.
Position Summary
Senior FPGA Designer with experience in the entire design flow for complex FPGA’s.
Responsibilities
Qualifications
Desired Qualifications
Education
Experience:
Comtech Telecommunications Corp. is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability protected veteran status or other characteristics protected by law.
