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Contract Asic Design Engineer Jobs (NOW HIRING)

ASIC/RTL Design Engineer Location: San Jose, CA Duration : 12 months plus JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA ...

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NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted ...

Jr. ASIC Design Engineer

Batavia, IL · On-site

$70K - $93K/yr

We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic ...

YOUR IMPACT Define, design and take end to end Front-End ownership of ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the ...

Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: - Write microarchitecture and/or design specifications - Design, implement, and debug complex logic ...

As an ASIC Design Engineer, your responsibilities span various aspects of SOC design:- Write microarchitecture and/or design specifications- Design, implement, and debug complex logic designs ...

We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from ...

As an ASIC Design Engineer, your responsibilities span various aspects of SOC design:- Write microarchitecture and/or design specifications- Design, implement, and debug complex logic designs ...

YOUR IMPACT Define, design and take end to end Front-End ownership of ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the ...

FPGA/ASIC Design Engineer

Camden, NJ · On-site

$124K - $171K/yr

Job #215247 Chipton-Ross is seeking an FPGA/ASIC Design Engineer for a contract opportunity in Camden, NJ. BASIC QUALIFICATIONS (REQUIRED SKILLS/EXPERIENCE) At least 3 year experience with proven ...

Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: - Write microarchitecture and/or design specifications - Design, implement, and debug complex logic ...

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Contract Asic Design Engineer information

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$94K

$150.2K

$202K

How much do contract asic design engineer jobs pay per year?

As of Jun 5, 2026, the average yearly pay for contract asic design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is the difference between Contract Asic Design Engineer vs Contract FPGA Design Engineer?

AspectContract Asic Design EngineerContract FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering, FPGA/ASIC design experienceBachelor's/Master's in Electrical Engineering or Computer Engineering, FPGA/ASIC design experience
Work EnvironmentSemiconductor companies, chip design firms, contract roles in hardware developmentSemiconductor companies, FPGA development firms, contract roles in hardware prototyping
Industry UsageUsed in chip manufacturing, integrated circuit design, hardware developmentUsed in prototyping, hardware acceleration, FPGA-based solutions

The main difference between a Contract Asic Design Engineer and a Contract FPGA Design Engineer lies in their focus areas. Asic engineers work on designing custom chips for mass production, while FPGA engineers develop flexible hardware solutions using programmable logic devices. Both roles require similar educational backgrounds and often overlap in industry applications, but their end goals and tools differ.

More about Contract Asic Design Engineer jobs
What cities are hiring for Contract Asic Design Engineer jobs? Cities with the most Contract Asic Design Engineer job openings:
What are the most commonly searched types of Asic Design Engineer jobs? The most popular types of Asic Design Engineer jobs are:
What states have the most Contract Asic Design Engineer jobs? States with the most job openings for Contract Asic Design Engineer jobs include:
Infographic showing various Contract Asic Design Engineer job openings in the United States as of May 2026, with employment types broken down into 80% Full Time, 18% Part Time, and 2% Contract. Highlights an 86% Physical, 9% Hybrid, and 5% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.
Principal ASIC Design Engineer (Starshield)

Principal ASIC Design Engineer (Starshield)

SpaceX

Hawthorne, CA

$200K - $285K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Posted 2 days ago


SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 143 frontline employees who took The Breakroom Quiz

13th of 59 rated aerospace companies


Job description

PRINCIPAL ASIC DESIGN ENGINEER (STARSHIELD)

Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As an ASIC Design Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. You will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace.

RESPONSIBILITIES:

  • Design digital ASICs and/or FPGAs for Starshield projects.
  • Evaluate architectural trade-offs based on features, performance requirements and system limitations. Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers to partition functions between hardware and software domains.
  • Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
  • Work closely with verification team to ensure all aspects of the design are covered and verified.
  • Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
  • Participate in silicon bring-up and validation. Assist in the development of automated test lab equipment for lab measurements.

BASIC QUALIFICATIONS:

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 8+ years of experience in RTL implementation and/or FPGA/ASIC development.

PREFERRED SKILLS AND EXPERIENCE:

  • Experience solving problems including clock domain crossings and power optimization.
  • Experience developing complex ASICs.
  • Experience with multicore CPU subsystem design.
  • Experience with standard bus protocols (e.g. AXI, AHB, etc.).
  • Experience with embedded processors.
  • Experience with high speed and low power design techniques.
  • Scripting skills (Python, TCL etc.).
  • Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II).
  • Ability to work in a dynamic environment with changing needs and requirements.
  • Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis.
  • Enjoy being challenged and learning new skills.

ADDITIONAL REQUIREMENTS:

  • Ability to work long hours and weekends as necessary to support critical milestones.
  • Willingness to travel for off-site testing.
  • An active TS-SCI clearance may provide the opportunity for you to work on sensitive SpaceX missions; if so, you will be subject to pre-employment drug and random drug and alcohol testing.

COMPENSATION AND BENEFITS:    

Pay range:    
Principal ASIC Design Engineer: $200,000.00 - $285,000.00/per year    
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. Those with an active clearance will receive a 10% differential, up to an additional $20,000 annually, once officially briefed into a classified program.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.


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