Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...
Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...
Principal ASIC Design Engineer
Carlsbad, CA · On-site
Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...
Principal ASIC Design Engineer
Carlsbad, CA · On-site
Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...
ASIC Verification Manager
San Jose, CA · On-site
$159K - $296K/yr
ASIC Verification Manager is responsible for managing and leading a diverse, global team of ASIC verification engineers, fostering a diverse and inclusive work environment. Developing and overseeing ...
ASIC Verification Manager
San Jose, CA · On-site
$159K - $296K/yr
ASIC Verification Manager is responsible for managing and leading a diverse, global team of ASIC verification engineers, fostering a diverse and inclusive work environment. Developing and overseeing ...
Lead ASIC DFT Engineer
San Jose, CA · On-site
Role: Lead ASIC DFT Engineer Location: Remote Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to ...
Quick apply
Lead ASIC DFT Engineer
San Jose, CA · On-site
Role: Lead ASIC DFT Engineer Location: Remote Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to ...
Lead ASIC DFT Engineer
San Jose, CA · Remote
Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Below is the detailed for your reference - Experience 10+ years of hands-on experience in ASIC Design-for-Test ...
Quick apply
Lead ASIC DFT Engineer
San Jose, CA · Remote
Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Below is the detailed for your reference - Experience 10+ years of hands-on experience in ASIC Design-for-Test ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard ...
ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI Engineers (8+ years) for permanent , full-time , onsite roles in Silicon Valley supporting advanced ...
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ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI Engineers (8+ years) for permanent , full-time , onsite roles in Silicon Valley supporting advanced ...
ASIC Verification Manager is responsible for managing and leading a diverse, global team of ASIC verification engineers, fostering a diverse and inclusive work environment. Developing and overseeing ...
ASIC Verification Manager is responsible for managing and leading a diverse, global team of ASIC verification engineers, fostering a diverse and inclusive work environment. Developing and overseeing ...
We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of ...
We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard ...
Sr. ASIC EDA Workflow Engineer
Sunnyvale, CA · On-site
The Sr. ASIC EDA Workflow Engineer will lead EDA tool flow management and engineering workflow development, optimizing and improving EDA workflows for ASIC design processes in a fast-paced, agile ...
Sr. ASIC EDA Workflow Engineer
Sunnyvale, CA · On-site
The Sr. ASIC EDA Workflow Engineer will lead EDA tool flow management and engineering workflow development, optimizing and improving EDA workflows for ASIC design processes in a fast-paced, agile ...
Lead ASIC DFT Engineer
San Jose, CA · On-site
Title - Lead ASIC DFT Engineer Location - San Jose, CA. Visa- USC/GC Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ...
Quick apply
Lead ASIC DFT Engineer
San Jose, CA · On-site
Title - Lead ASIC DFT Engineer Location - San Jose, CA. Visa- USC/GC Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard ...
ASIC Design-for-Test (DFT)
San Jose, CA · On-site
Role: Lead ASIC DFT Engineer Location: San Jose, CA Work Setup: Remote, PST time zone Nbr of openings: 4 positions. Visa type: Any Visa who can work in PST time zone Position type: W2 or C2C ...
Quick apply
ASIC Design-for-Test (DFT)
San Jose, CA · On-site
Role: Lead ASIC DFT Engineer Location: San Jose, CA Work Setup: Remote, PST time zone Nbr of openings: 4 positions. Visa type: Any Visa who can work in PST time zone Position type: W2 or C2C ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard ...
Senior Manager, ASIC Design
Santa Clara, CA · On-site
Reporting to the Senior Director, ASIC Engineering, you will manage a team and oversee the end-to-end design and development of high-performance ASICs, ensuring technical excellence, on-time project ...
Senior Manager, ASIC Design
Santa Clara, CA · On-site
Reporting to the Senior Director, ASIC Engineering, you will manage a team and oversee the end-to-end design and development of high-performance ASICs, ensuring technical excellence, on-time project ...
Senior ASIC Design Engineer
Santa Clara, CA · On-site
We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of ...
Senior ASIC Design Engineer
Santa Clara, CA · On-site
We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer to join our dynamic group. In this role, you will develop custom SoCs that drive the performance ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer to join our dynamic group. In this role, you will develop custom SoCs that drive the performance ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard ...
Asic information
See salary details
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
How much do asic jobs pay per year?
What are some common challenges faced by ASIC engineers during the chip design and verification process?
What is an ASIC?
What is the difference between Asic vs FPGA Engineer?
| Aspect | Asic | FPGA Engineer |
|---|---|---|
| Required Credentials | Bachelor's or higher in Electrical Engineering, VLSI Design, or related fields; certifications like Certified FPGA Designer are common | Similar educational background; often the same certifications apply, especially in digital design |
| Work Environment | Designing and developing custom integrated circuits in a semiconductor lab or design house | Developing programmable logic solutions using FPGA boards in labs or on-site environments |
| Industry Usage | Used in high-volume, performance-critical applications like consumer electronics, automotive, and telecommunications | Common in prototyping, testing, and specialized applications requiring flexibility |
In summary, Asic and FPGA engineers share similar educational backgrounds and certifications. Asic engineers focus on designing custom chips for high-volume applications, while FPGA engineers work on programmable logic devices for flexible, rapid prototyping and testing. Both roles are vital in the semiconductor and electronics industries, often overlapping in skills and tools used.
What are ASIC engineers?
What are the highest paying ASIC companies?
What are the key skills and qualifications needed to thrive as an ASIC (Application-Specific Integrated Circuit) Engineer, and why are they important?
Is ASIC a good career?
How to become an ASIC?

Other
Re-posted 21 days ago
Job description
Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor device modeling. Requirements: Principal Engineer will be responsible for design and development from multiple ASIC blocks to a complete Core/Chip in communications/digital signal processing (DSP) IC products. These include building blocks/Cores for communication functions.
The responsibility includes working with system engineering or product marketing department to close design specifications, define block/core/chip architectures, carry out and verify the design. Need to Have: Communications/DSP algorithm and efficient implementations. System-on-the-chip architectures Knowledge and hand-on experience from industry ASIC design flow including RTL coding, debugging/verification, synthesizing and supporting timing closure.
Design experience in Communications/DSP building blocks and/or SOC functional modules. Experience with design tools such as NCSIM (and/or VCS), Cadence RC or Synopsys DC compiler, Experience with multiple IC tape-out in industry. Experience in chip bring up and performance measurement for IC and systems in laboratory to characterize and debug building blocks MS in EE with 12 years of experience or Ph.D
in EE with 10 years of experience.