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Asic Jobs (NOW HIRING)

Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Type :- */W2 Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are ...

Principal ASIC Design Engineer

Austin, TX · On-site

$180K - $220K/yr

Atom Computing is seeking a Principal ASIC Designer to lead the development of critical technologies that power our quantum computers. In this role, you will own end-to-end design strategy-from ...

Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...

Understand ASIC logic design. Knowledge of low power design and UPF. Proficiency in scripting languages (Shell, Perl or Python). Basic knowledge on common SOC components, e.g. CPU, fabric ...

ASIC Verification Manager is responsible for managing and leading a diverse, global team of ASIC verification engineers, fostering a diverse and inclusive work environment. Developing and overseeing ...

JB061568 - Lead ASIC DFT Engineer

San Jose, CA · On-site

$194K/yr

Skills ASIC DFT, Visa Types Green Card, US Citiz.. Required Skills & Qualifications * Strong hands-on experience in ASIC DFT with end-to-end ownership. * Solid understanding of DFT fundamentals ...

We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for large ...

JB061568 - Lead ASIC DFT Engineer

San Jose, CA · On-site

$194K/yr

Skills ASIC DFT, Visa Types Green Card, US Citiz.. Required Skills & Qualifications * Strong hands-on experience in ASIC DFT with end-to-end ownership. * Solid understanding of DFT fundamentals ...

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Asic information

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$94K

$150.2K

$202K

How much do asic jobs pay per year?

As of Jun 27, 2026, the average yearly pay for asic in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What are some common challenges faced by ASIC engineers during the chip design and verification process?

ASIC engineers often encounter challenges such as balancing power, performance, and area constraints while meeting tight project deadlines. Ensuring design correctness through thorough verification and debugging complex issues can be demanding, especially when integrating multiple IP blocks. Collaboration with cross-functional teams—including hardware, software, and test engineers—is essential to resolve challenges efficiently. Staying updated with evolving EDA tools and methodologies also plays a key role in overcoming these hurdles.

What is the difference between Asic vs FPGA Engineer?

AspectAsicFPGA Engineer
Required CredentialsBachelor's or higher in Electrical Engineering, VLSI Design, or related fields; certifications like Certified FPGA Designer are commonSimilar educational background; often the same certifications apply, especially in digital design
Work EnvironmentDesigning and developing custom integrated circuits in a semiconductor lab or design houseDeveloping programmable logic solutions using FPGA boards in labs or on-site environments
Industry UsageUsed in high-volume, performance-critical applications like consumer electronics, automotive, and telecommunicationsCommon in prototyping, testing, and specialized applications requiring flexibility

In summary, Asic and FPGA engineers share similar educational backgrounds and certifications. Asic engineers focus on designing custom chips for high-volume applications, while FPGA engineers work on programmable logic devices for flexible, rapid prototyping and testing. Both roles are vital in the semiconductor and electronics industries, often overlapping in skills and tools used.

Do you have to be a citizen to work for ASIC?

For an ASIC-related role, citizenship requirements depend on the employer and the specific position. Some positions may require legal work authorization or permanent residency, especially for government or security-sensitive roles, while others may be open to non-citizens with valid work visas. It is important to review the job posting or contact the employer for specific eligibility criteria.

What are ASIC engineers?

ASIC engineers are professionals who design, develop, and test Application-Specific Integrated Circuits (ASICs). These are specialized microchips created for a particular application or product, such as smartphones, networking equipment, or automotive systems. ASIC engineers work on the entire chip design process, including architecture, logic design, verification, and sometimes physical layout. Their expertise ensures that the chips are efficient, reliable, and tailored to meet specific performance requirements.

What does an ASIC do?

An ASIC (Application-Specific Integrated Circuit) is a specialized hardware chip designed for a particular application, such as cryptocurrency mining or telecommunications. ASIC engineers develop, test, and optimize these chips, often requiring knowledge of digital design, hardware description languages, and electronic testing tools.

What are the key skills and qualifications needed to thrive as an ASIC (Application-Specific Integrated Circuit) Engineer, and why are they important?

To thrive as an ASIC Engineer, you need a solid background in electrical or computer engineering, digital design, and experience with hardware description languages like Verilog or VHDL. Familiarity with EDA tools such as Cadence or Synopsys and relevant certifications (e.g., in ASIC design or verification) are highly valuable. Strong analytical thinking, attention to detail, and effective teamwork skills set top performers apart in this role. These competencies are crucial for developing reliable, high-performance chips that meet complex specifications and project goals.

Is ASIC a good career?

An ASIC (Application-Specific Integrated Circuit) design engineer or developer is a specialized role in electronics and semiconductor industries. It offers opportunities for high technical skill development, competitive salaries, and involvement in cutting-edge technology, but it also requires strong knowledge of digital design, hardware description languages, and often long project cycles. Overall, it can be a rewarding career for those interested in hardware design and engineering.

How much do ASIC engineers get paid?

ASIC engineers typically earn between $80,000 and $150,000 annually, depending on experience, location, and company size. Senior roles or those with specialized skills in hardware description languages and verification tools can command higher salaries.
More about Asic jobs
What cities are hiring for Asic jobs? Cities with the most Asic job openings:
What are the most commonly searched types of Asic jobs? The most popular types of Asic jobs are:
What states have the most Asic jobs? States with the most job openings for Asic jobs include:
Infographic showing various Asic job openings in the United States as of June 2026, with employment types broken down into 3% Internship, 78% Full Time, 3% Part Time, 13% Contract, and 3% Nights. Highlights an 89% Physical, 7% Hybrid, and 4% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.
ASIC DFT Engineer

Other

Posted 8 days ago


Job description

Title - Lead ASIC DFT Engineer
Location – Remote (must be aligned with PST time zone)
Type :- */W2
Experience
10+ years of hands-on experience in ASIC Design-for-Test (DFT)
Role Summary
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.
The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.
Key Responsibilities
  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.
Required Skills & Qualifications
  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.
Preferred Experience
  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.
Regards
Nirdosh Singh
Sr. Account Manager | Tanisha Systems Inc.
Phone: 732-377-3299 x 599
Email: nirdosh@tanishasystems.com
Web: www.tanishasystems.com
99 Wood Ave South, Suite # 308, Iselin, NJ 08830
LinkedIn :- https://www.linkedin.com/in/nirdosh-soami-rajput/
About Tanisha Systems, Inc.
Tanisha Systems, founded in 2002 in Massachusetts-*, is a leading provider of Custom Application Development and end-to-end IT Services to clients globally. We use a client-centric engagement model that combines local on-site and off-site resources with the cost, global expertise and quality advantages of off-shore operations. We deliver Custom Application Development, Application Modernization, Business Process Outsourcing and Professional IT Services from office locations in * and *.
Tanisha Systems services clients in Government, Banking & Financial Markets, Insurance, Healthcare, Retail & Consumer Goods, Energy & Utilities, Life Sciences, Telecom, Manufacturing and Transportation Industries around the globe. Our engagement model provides a flexible operational environment that empowers our clients with the right levels of control.
Want to read more about Tanisha Systems? Visit us at www.tanishasystems.com
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