SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At ...
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At ...
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine, CA · On-site
$160K - $220K/yr
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At ...
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine, CA · On-site
$160K - $220K/yr
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At ...
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Sunnyvale, CA · On-site
$170K - $230K/yr
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At ...
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Sunnyvale, CA · On-site
$170K - $230K/yr
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At ...
Principal ASIC Design Engineer
Austin, TX · On-site
$180K - $220K/yr
MS or PhD in Electrical Engineering or a related field. * 10+ years of post-degree experience in hardware engineering, specifically in ASIC/SoC environments. Qualifications * Have gone through 2 or ...
Principal ASIC Design Engineer
Austin, TX · On-site
$180K - $220K/yr
MS or PhD in Electrical Engineering or a related field. * 10+ years of post-degree experience in hardware engineering, specifically in ASIC/SoC environments. Qualifications * Have gone through 2 or ...
Wireless SOC Verification Engineer
Irvine, CA · On-site
$146K - $178.20K/yr
As part of the Wireless SOC team, you will have the opportunity to verify complex SOCs. Our team ... Proven track record of working full ASIC cycle from concept to tape-out to bring-up, including test ...
Wireless SOC Verification Engineer
Irvine, CA · On-site
$146K - $178.20K/yr
As part of the Wireless SOC team, you will have the opportunity to verify complex SOCs. Our team ... Proven track record of working full ASIC cycle from concept to tape-out to bring-up, including test ...
Principal ASIC Design Engineer
Boulder, CO · On-site
$180K - $220K/yr
MS or PhD in Electrical Engineering or a related field. * 10+ years of post-degree experience in hardware engineering, specifically in ASIC/SoC environments. Qualifications * Have gone through 2 or ...
Principal ASIC Design Engineer
Boulder, CO · On-site
$180K - $220K/yr
MS or PhD in Electrical Engineering or a related field. * 10+ years of post-degree experience in hardware engineering, specifically in ASIC/SoC environments. Qualifications * Have gone through 2 or ...
Principal ASIC Design Engineer
Austin, TX · On-site
$180K - $220K/yr
MS or PhD in Electrical Engineering or a related field. * 10+ years of post-degree experience in hardware engineering, specifically in ASIC/SoC environments. Qualifications * Have gone through 2 or ...
Principal ASIC Design Engineer
Austin, TX · On-site
$180K - $220K/yr
MS or PhD in Electrical Engineering or a related field. * 10+ years of post-degree experience in hardware engineering, specifically in ASIC/SoC environments. Qualifications * Have gone through 2 or ...
Principal ASIC Design Engineer
$180K - $220K/yr
MS or PhD in Electrical Engineering or a related field. * 10+ years of post-degree experience in hardware engineering, specifically in ASIC/SoC environments. Qualifications * Have gone through 2 or ...
Quick apply
Principal ASIC Design Engineer
$180K - $220K/yr
MS or PhD in Electrical Engineering or a related field. * 10+ years of post-degree experience in hardware engineering, specifically in ASIC/SoC environments. Qualifications * Have gone through 2 or ...
The ideal candidate will have strong experience in pre-silicon ASIC/SoC design , controller architecture, RTL development, and design debug. This role requires end-to-end ownership of controller ...
The ideal candidate will have strong experience in pre-silicon ASIC/SoC design , controller architecture, RTL development, and design debug. This role requires end-to-end ownership of controller ...
ASIC/SOC CAD Engineer
Mountain View, CA · On-site +1
$175K - $362.50K/yr
The ASIC/SOC Physically Design CAD Engineer will be responsible for creating and maintaining our CAD flow and infrastructure to produce performant and functionally correct silicon for MatX products ...
ASIC/SOC CAD Engineer
Mountain View, CA · On-site +1
$175K - $362.50K/yr
The ASIC/SOC Physically Design CAD Engineer will be responsible for creating and maintaining our CAD flow and infrastructure to produce performant and functionally correct silicon for MatX products ...
Principal ASIC Design Engineer
$180K - $220K/yr
Experience & Education MS or PhD in Electrical Engineering or a related field. 10+ years of post-degree experience in hardware engineering, specifically in ASIC/SoC environments. Qualifications Have ...
Principal ASIC Design Engineer
$180K - $220K/yr
Experience & Education MS or PhD in Electrical Engineering or a related field. 10+ years of post-degree experience in hardware engineering, specifically in ASIC/SoC environments. Qualifications Have ...
Principal ASIC Design Engineer
$180K - $220K/yr
MS or PhD in Electrical Engineering or a related field. * 10+ years of post-degree experience in hardware engineering, specifically in ASIC/SoC environments. Qualifications * Have gone through 2 or ...
Quick apply
Principal ASIC Design Engineer
$180K - $220K/yr
MS or PhD in Electrical Engineering or a related field. * 10+ years of post-degree experience in hardware engineering, specifically in ASIC/SoC environments. Qualifications * Have gone through 2 or ...
Digital ASIC Design Engineer
San Diego, CA · On-site
$98.50K - $147.70K/yr
As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize ... This is a great opportunity to join a fast-paced SoC team responsible for RTL Design, flows and ...
Digital ASIC Design Engineer
San Diego, CA · On-site
$98.50K - $147.70K/yr
As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize ... This is a great opportunity to join a fast-paced SoC team responsible for RTL Design, flows and ...
Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance. * Develop reusable testbench, constrained-random/directed testcases, and ...
Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance. * Develop reusable testbench, constrained-random/directed testcases, and ...
ASIC/SoC Design Verification Engineer
$110K - $300K/yr
Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance * Develop reusable testbench, constrained-random/directed test cases, and ...
ASIC/SoC Design Verification Engineer
$110K - $300K/yr
Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance * Develop reusable testbench, constrained-random/directed test cases, and ...
ASIC/SoC Design Verification Engineer
San Jose, CA · On-site
$110K - $300K/yr
Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance * Develop reusable testbench, constrained-random/directed test cases, and ...
ASIC/SoC Design Verification Engineer
San Jose, CA · On-site
$110K - $300K/yr
Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance * Develop reusable testbench, constrained-random/directed test cases, and ...
ASIC/SOC CAD Engineer
Mountain View, CA · On-site
$175K - $362.50K/yr
The ASIC/SOC Physically Design CAD Engineer will be responsible for creating and maintaining our CAD flow and infrastructure to produce performant and functionally correct silicon for MatX products ...
ASIC/SOC CAD Engineer
Mountain View, CA · On-site
$175K - $362.50K/yr
The ASIC/SOC Physically Design CAD Engineer will be responsible for creating and maintaining our CAD flow and infrastructure to produce performant and functionally correct silicon for MatX products ...
Job Title: Senior Physical Design / STA Engineer - W2
$152.70K - $157.20K/yr
The ideal candidate will have expertise in timing closure, synthesis, place & route, and signoff activities for high-performance ASIC/SoC designs. Responsibilities * Perform full-chip and block-level ...
New
Job Title: Senior Physical Design / STA Engineer - W2
$152.70K - $157.20K/yr
The ideal candidate will have expertise in timing closure, synthesis, place & route, and signoff activities for high-performance ASIC/SoC designs. Responsibilities * Perform full-chip and block-level ...
New
Influence and evolve ASIC / SoC CAD tools, flows, and design methodologies across design construction, optimization, and signoff * Support blocklevel and fullchip integration , enabling highquality ...
Influence and evolve ASIC / SoC CAD tools, flows, and design methodologies across design construction, optimization, and signoff * Support blocklevel and fullchip integration , enabling highquality ...
Asic Soc information
See salary details
$140K - $147.2K
4% of jobs
$147.2K - $154.5K
12% of jobs
$158.7K is the 25th percentile. Wages below this are outliers.
$154.5K - $161.7K
16% of jobs
$161.7K - $168.9K
16% of jobs
The median wage is $170.4K / yr.
$168.9K - $176.1K
13% of jobs
$176.1K - $183.4K
8% of jobs
$189.8K is the 75th percentile. Wages above this are outliers.
$183.4K - $190.6K
7% of jobs
$190.6K - $197.8K
6% of jobs
$197.8K - $205K
7% of jobs
$205K - $212.3K
5% of jobs
$212.3K - $219.5K
5% of jobs
$140K
$177.7K
$219.5K
How much do asic soc jobs pay per year?
What is the difference between Asic Soc vs FPGA Designer?
| Aspect | Asic Soc | FPGA Designer |
|---|---|---|
| Required Skills | Hardware design, embedded systems, VHDL/Verilog, ASIC development | Hardware description languages, FPGA architecture, VHDL/Verilog |
| Work Environment | Semiconductor companies, integrated circuit design labs | Electronics firms, prototyping labs, FPGA development environments |
| Industry Usage | Consumer electronics, automotive, telecommunications | Prototyping, testing, low-volume production |
Both Asic Soc and FPGA Designer roles involve hardware description languages and embedded systems, but Asic Soc engineers focus on designing integrated circuits for mass production, while FPGA Designers work on flexible, reprogrammable hardware for testing and prototyping. The skills overlap makes them common choices for hardware development in electronics industries.

$160K - $220K/yr
Other
Medical, Dental, Vision, Life, Retirement, PTO
Posted 3 days ago
SpaceX rating
8.7
Based on 142 frontline employees who took The Breakroom Quiz
12th of 59 rated aerospace companies
Job description
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
- Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
- Develop/improve physical design methodologies and automation scripts for various implementation steps
- Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
- Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
- Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop
BASIC QUALIFICATIONS:
- Bachelor's degree in electrical engineering, computer engineering or computer science
- 5+ years of ASIC and/or physical design flow development experience in industry
PREFERRED SKILLS AND EXPERIENCE:
- Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
- Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
- Knowledge of deep sub-micron FinFET and CMOS solid state physics
- Knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
- Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
- Familiar with CMOS analog circuit and physical design
- Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
- Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
- Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment
ADDITIONAL REQUIREMENTS:
- Ability to work extended hours and weekends as needed to meet critical project milestones
COMPENSATION AND BENEFITS:
Pay range:
Physical Design Engineer/Senior: $160,000.00 - $220,000.00/per year
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.
About SpaceX
Sourced by ZipRecruiter
Industry
Accounting services
Company size
1,001 - 5,000 Employees
Headquarters location
Hawthorne, CA, US
Year founded
2002