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Asic Soc Jobs (NOW HIRING)

TetraMem INC

ASIC RTL/SoC Design Engineer

Fremont, CA · On-site

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs. * Integrate and validate IP blocks within the larger system, ensuring ...

Amazon

Sr. Technical Program Manager, ASIC

Austin, TX · On-site

The Amazon LEO team is looking for a Sr. Technical Program Manager with experience in complex ASIC/SOC development of managing various phases of pre-silicon such as architecture, front end design ...

TetraMem Inc

ASIC RTL/SoC Design Engineer

San Jose, CA · On-site

$110K - $300K/yr

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs * Integrate and validate IP blocks within the larger system, ensuring ...

Marvell

Senior Manager, ASIC Design

Santa Clara, CA

Strong knowledge across the full ASIC/SOC development cycle from microarchitecture development to tape-out in advanced process technologies * Outstanding technical expertise in microarchitecture ...

Bolt Graphics

RTL Design Tech Lead (ASIC/SoC)

Sunnyvale, CA · On-site

$220K - $250K/yr

About the role: We're looking for a seasoned RTL Design Tech Lead to drive micro-architecture, RTL development, and technical execution for complex ASIC/SoC programs. This role combines deep hands-on ...

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How much do asic soc jobs pay per year?

As of Jul 10, 2026, the average yearly pay for asic soc in the United States is $177,653.00, according to ZipRecruiter salary data. Most workers in this role earn between $159,000.00 and $195,000.00 per year, depending on experience, location, and employer.

What is the difference between Asic Soc vs FPGA Designer?

AspectAsic SocFPGA Designer
Required SkillsHardware design, embedded systems, VHDL/Verilog, ASIC developmentHardware description languages, FPGA architecture, VHDL/Verilog
Work EnvironmentSemiconductor companies, integrated circuit design labsElectronics firms, prototyping labs, FPGA development environments
Industry UsageConsumer electronics, automotive, telecommunicationsPrototyping, testing, low-volume production

Both Asic Soc and FPGA Designer roles involve hardware description languages and embedded systems, but Asic Soc engineers focus on designing integrated circuits for mass production, while FPGA Designers work on flexible, reprogrammable hardware for testing and prototyping. The skills overlap makes them common choices for hardware development in electronics industries.

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What cities are hiring for Asic Soc jobs? Cities with the most Asic Soc job openings:
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Asic Soc jobs near you
Infographic showing various Asic Soc job openings in the United States as of July 2026, with employment types broken down into 96% Full Time, 1% Part Time, 2% Contract, and 1% Summer. Highlights an 89% Physical, 6% Hybrid, and 5% Remote job distribution, with an average salary of $177,653 per year, or $85.4 per hour.
ASIC RTL/SoC Design Engineer

ASIC RTL/SoC Design Engineer

TetraMem INC

Fremont, CA • On-site

Full-time

Medical, Retirement, PTO

Re-posted 2 days ago

Job description

Company Description
TetraMem is a fast-growing well-funded startup company working on the next generation of computing platforms with unique ReRAM-based in-memory computing technologies. We are hiring in multiple positions from software to hardware.
We offer a very competitive compensation, commensurate with experience, and a full benefits package including medical, professional PTO, 401k, and other perks.
Job Description
  • Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs.
  • Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility.
  • Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs.
  • Collaborate closely with the backend team, participating in RTL coding, implementation, and synthesis stages to ensure successful tapeout.
  • Develop and maintain reusable internal intellectual properties (IPs) tailored for AI and/or in-memory computing applications.
  • Provide crucial support for Post-Si testing and validation, diagnosing and rectifying issues to ensure the overall functionality and quality of the product.
  • Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best practices to foster their professional growth.
  • Contribute to design reviews and cross-functional discussions, offering insights and recommendations to enhance product performance and reliability.
  • Stay up-to-date with industry trends and advancements in RTL design methodologies, integrating innovative techniques to improve product quality and efficiency.
  • Collaborate with cross-functional teams, including software, architecture, and verification teams, to achieve cohesive and successful product development and delivery.

Qualifications
  • MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design
  • Experience with Verilog and system Verilog
  • Experience with VCS, Verdi or other industry standard tools
  • Experience with pre-layout simulation and post-layout simulation
  • Understanding of the design flow. Ability to work with the backend team
  • Familiarity with AMBA APB AXI Protocol
  • Familiarity with RISC/Arm or other core architectures
  • Ability to create innovative architecture and solutions to customer requirements
  • Ability to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team.

Experience in one or more of the following areas considered a strong plus:
  • FPGA/ASIC design of image processing systems
  • Working knowledge of SoC architecture such as CPU, GPU or accelerators
  • Familiarity with: UVM, place-and-route, STA, EM/IR/Power

Additional Information
All your information will be kept confidential according to EEO guidelines.

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