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81 Meta Design Verification Engineer Jobs Hiring Near You

Epitec

Design Verification Engineer III

Sunnyvale, CA · On-site

$159K - $194K/yr

Design Verification Engineer III Contract Duration: 6 months, possible extension Location ... Previous Meta experience preferred. Education * BS in Electrical/Computer Engineering or Computer ...

Meta

ASIC Engineer, Design Verification

Sunnyvale, CA · On-site +1

$114K/yr

Meta is hiring an ASIC Design Verification Engineer within the Infrastructure Silicon organization. We are looking for individuals with experience in Design Verification to build IP and System on ...

Meta

ASIC Engineer, Design Verification

Austin, TX · On-site +1

$114K/yr

Meta is hiring an ASIC Design Verification Engineer within the Infrastructure Silicon organization. We are looking for individuals with experience in Design Verification to build IP and System on ...

Abode TechZone

Design Verification Engineer

Sunnyvale, CA · Hybrid

$159K - $194K/yr

Design Verification Engineer Location: Sunnyvale, CA Job Type: Full-time Work Arrangement: Onsite role, Work from Client Office - 5 days a week Interview: Two rounds of Video interview We are seeking ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer ID: 1063 Location: Austin, TX More about this job > Description Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position ...

COGENT Infotech

Design Verification Engineer

Saratoga, CA · On-site

$150K - $183K/yr

Design Verification Engineer Location: Saratoga, CA (Onsite)-5 days We are seeking a Design Verification Engineer with 8+ years of experience in semiconductor verification. The ideal candidate will ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer ID: 1058 Location: Austin, TX More about this job > Description Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position ...

Sivaltech

Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

Design Verification Engineer Location: Bay Area, CA (Onsite/Hybrid) Experience: 8+ Years Job Summary We are seeking an experienced Design Verification Engineer with strong expertise in ASIC/SoC ...

HCP ONE LLC

Design Verification Engineer

San Jose, CA · On-site

$159K - $194K/yr

Design Verification Engineer Location: San Jose, CA Experience: 8+ Years Type: Contract Description: This requirement is for a Senior Design Verification (DV) Engineer focused on verifying complex ...

Ursus, Inc.

Design Verification Engineer

Sunnyvale, CA · Hybrid

$73 - $83/hr

Design Verification Engineer LOCATION: Sunnyvale, CA (Hybrid; 3 days in office/week) DURATION: 6 months with possible extension PAY RANGE: $73 - $83/hr. TOP 3 SKILLS: * SystemVerilog / UVM testbench ...

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Infographic showing various Design Verification Engineer job openings at Meta in the United States as of August 2026, with employment types broken down into 100% Full Time. Highlights an 82% Physical, and 18% Remote job distribution.

Design Verification Engineer III

Epitec

Sunnyvale, CA • On-site

$159K - $194K/yr

Contractor

Posted 21 days ago

Job description

  • Location: Sunnyvale, California
  • Type: Contract
  • Job #105702

Job Title: Design Verification Engineer III
Contract Duration: 6 months, possible extension
Location: Sunnyvale, CA
Work Arrangement: Hybrid (3 days onsite)
Summary
Design Verification Engineer for wearables silicon accelerator IPs - testbench development, coverage-driven verification, RTL debug, and power/performance measurement.
Responsibilities
  • Develop and execute verification plans for RTL blocks/IPs across the subsystem.
  • Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests.
  • Drive functional coverage and assertion (SVA) closure; run and triage regressions.
  • Perform power/performance measurement across design stages using PPA RTL, PtPx tool; correlate results with post silicon and feed back to design/power-modeling teams.
  • Build power/perf dashboard for tracking and publishing
  • Debug RTL failures (waveform/Verdi) and provide actionable feedback to the design team/verification team.
  • Contribute to automation of verification/regression and power/performance measurement flows (Python).

Minimum Qualifications
  • Proven SystemVerilog + UVM verification experience (testbench architecture, sequences, drivers/monitors).
  • Functional coverage, constrained-random, and assertion-based verification (SVA); coverage closure.
  • Strong RTL debug with industry simulators (VCS / Xcelium / Questa) and waveform tools (Verdi).
  • Working knowledge of RTL design principles and digital design fundamentals.
  • Proficiency in Python (or Perl) scripting for automation.

Preferred Qualifications
  • Experience with power measurement tools - PrimeTime PX (PTPX) or equivalent (e.g., PrimePower).
  • Low-power / power-aware verification (UPF, power-aware sim) in advanced nodes (7nm and below).
  • Formal verification and/or emulation (Palladium / Zebu) experience.
  • Familiarity with the RTL-to-GDSII flow.
  • Data analysis / ML approaches for coverage or debug triage.
  • Previous Meta experience preferred.

Education
  • BS in Electrical/Computer Engineering or Computer Science required
  • MS preferred (not required).

Top 3 Must-Have Skills
  • SystemVerilog / UVM testbench development.
  • Functional coverage + assertion-based verification and coverage closure.
  • RTL debug (VCS/Xcelium) + Python automation; power/perf measurement.

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