We are seeking a Senior Digital VLSI Design Engineer with deep expertise in Synthesis, DFT, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) sign-off for high speed complex IPs to be ...
We are seeking a Senior Digital VLSI Design Engineer with deep expertise in Synthesis, DFT, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) sign-off for high speed complex IPs to be ...
We are seeking a Senior Digital VLSI Design Engineer with deep expertise in Synthesis, DFT, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) sign-off for high speed complex IPs to be ...
We are seeking a Senior Digital VLSI Design Engineer with deep expertise in Synthesis, DFT, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) sign-off for high speed complex IPs to be ...
Senior Applied Machine Learning Engineer - VLSI Design
Santa Clara, CA · On-site
$152 - $230/hr
Work on applications ranging from silicon data analysis, manufacturing process variation analysis, VLSI circuit design, timing, and agent‑driven design exploration and agent flow optimization.
Senior Applied Machine Learning Engineer - VLSI Design
Santa Clara, CA · On-site
$152 - $230/hr
Work on applications ranging from silicon data analysis, manufacturing process variation analysis, VLSI circuit design, timing, and agent‑driven design exploration and agent flow optimization.
Work on applications ranging from silicon data analysis, manufacturing process variation analysis, VLSI circuit design, timing, and agent-driven design exploration and agent flow optimization.
Work on applications ranging from silicon data analysis, manufacturing process variation analysis, VLSI circuit design, timing, and agent-driven design exploration and agent flow optimization.
Staff VLSI Design Engineer
Milpitas, CA · On-site
RTL design and verification in Verilog, RTL linting, clock domain crossing (CDC) analysis, design integration, synthesis, DFT, timing analysis and closure * Balance design trade-offs with modularity ...
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Staff VLSI Design Engineer
Milpitas, CA · On-site
RTL design and verification in Verilog, RTL linting, clock domain crossing (CDC) analysis, design integration, synthesis, DFT, timing analysis and closure * Balance design trade-offs with modularity ...
New
Senior VLSI CAD Software Engineer
Austin, TX · On-site
$168 - $264.50/hr
Senior VLSI CAD Software Engineer page is loaded## Senior VLSI CAD Software Engineerlocations: US, CA, Santa Clara: US, MA, Westford: US, TX, Austin: US, OR, Hillsboro: US, NC, Durhamtime type: Full ...
Senior VLSI CAD Software Engineer
Austin, TX · On-site
$168 - $264.50/hr
Senior VLSI CAD Software Engineer page is loaded## Senior VLSI CAD Software Engineerlocations: US, CA, Santa Clara: US, MA, Westford: US, TX, Austin: US, OR, Hillsboro: US, NC, Durhamtime type: Full ...
Qualcomm Technologies Inc is a leader in the technology sector, focusing on developing tools and methodologies for VLSI design. The role involves developing CAD tools for emulation, optimizing ...
Qualcomm Technologies Inc is a leader in the technology sector, focusing on developing tools and methodologies for VLSI design. The role involves developing CAD tools for emulation, optimizing ...
Work on applications ranging from silicon data analysis, manufacturing process variation analysis, VLSI circuit design, timing, and agent-driven design exploration and agent flow optimization.
Work on applications ranging from silicon data analysis, manufacturing process variation analysis, VLSI circuit design, timing, and agent-driven design exploration and agent flow optimization.
Work on applications ranging from silicon data analysis, manufacturing process variation analysis, VLSI circuit design, timing, and agent-driven design exploration and agent flow optimization.
Work on applications ranging from silicon data analysis, manufacturing process variation analysis, VLSI circuit design, timing, and agent-driven design exploration and agent flow optimization.
We are seeking a Senior R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
We are seeking a Senior R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
Staff VLSI Design Engineer
Milpitas, CA · On-site
$147K - $251K/yr
RTL design and verification in Verilog, RTL linting, clock domain crossing (CDC) analysis, design integration, synthesis, DFT, timing analysis and closure * Balance design trade-offs with modularity ...
Staff VLSI Design Engineer
Milpitas, CA · On-site
$147K - $251K/yr
RTL design and verification in Verilog, RTL linting, clock domain crossing (CDC) analysis, design integration, synthesis, DFT, timing analysis and closure * Balance design trade-offs with modularity ...
ASIC verification engineer
Roseville, CA · On-site
Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through software developed for component and ...
ASIC verification engineer
Roseville, CA · On-site
Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through software developed for component and ...
We are seeking a Senior R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
We are seeking a Senior R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through software developed for component and ...
Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through software developed for component and ...
Senior ASIC verification engineer
Roseville, CA · On-site
$153.50 - $310.50/hr
Senior ASIC Verification Engineer Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through ...
Senior ASIC verification engineer
Roseville, CA · On-site
$153.50 - $310.50/hr
Senior ASIC Verification Engineer Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through ...
We are seeking a Senior R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
We are seeking a Senior R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
Software R&D Engineer, VLSI Physical Design - New College Grad 2026
Austin, TX · Hybrid
$134K - $138K/yr
We are seeking a R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
Software R&D Engineer, VLSI Physical Design - New College Grad 2026
Austin, TX · Hybrid
$134K - $138K/yr
We are seeking a R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
We are seeking a Senior R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
We are seeking a Senior R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
Software R&D Engineer, VLSI Physical Design - New College Grad 2026
Santa Clara, CA · Hybrid
$159K - $164K/yr
We are seeking a R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
Software R&D Engineer, VLSI Physical Design - New College Grad 2026
Santa Clara, CA · Hybrid
$159K - $164K/yr
We are seeking a R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
Software R&D Engineer, VLSI Physical Design - New College Grad 2026
Santa Clara, CA · Hybrid
$159K - $164K/yr
We are seeking a R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
Software R&D Engineer, VLSI Physical Design - New College Grad 2026
Santa Clara, CA · Hybrid
$159K - $164K/yr
We are seeking a R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
Vlsi Design information
See salary details
$95K - $99.2K
0% of jobs
$99.2K - $103.5K
0% of jobs
$103.5K - $107.7K
0% of jobs
$107.7K - $111.9K
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$111.9K - $116.1K
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$116.1K - $120.4K
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$120.4K - $124.6K
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$124.6K - $128.8K
0% of jobs
$128.8K - $133K
1% of jobs
$135.4K is the 25th percentile. Wages below this are outliers.
$133K - $137.3K
43% of jobs
The median wage is $137.7K / yr.
$137.3K - $141.5K
56% of jobs
$95K
$141.5K
How much do vlsi design jobs pay per year?
What is a VLSI design?
A VLSI (Very Large Scale Integration) Design job involves designing and developing integrated circuits (ICs) by integrating millions or billions of transistors onto a single chip. Engineers in this role work on various stages of chip design, including RTL design, verification, synthesis, physical design, and testing. They utilize hardware description languages (HDLs) like Verilog and VHDL, along with Electronic Design Automation (EDA) tools. VLSI engineers are crucial in industries such as consumer electronics, automotive, telecommunications, and artificial intelligence. This field requires strong knowledge of digital electronics, semiconductor physics, and circuit design.
What are the typical day-to-day responsibilities of a VLSI design engineer?
VLSI Design engineers typically engage in activities such as circuit design, schematic capture, simulation, verification, and layout optimization, all while collaborating with cross-functional teams like verification, testing, and product engineering. They are often responsible for writing and debugging hardware description languages, analyzing timing and power constraints, and ensuring compliance with design specifications. Regular review meetings and collaboration with other engineers help address challenges and integrate feedback for design improvements. The dynamic nature of this role offers exposure to cutting-edge technology and hands-on experience with the full lifecycle of chip development.
What are the key skills and qualifications needed to thrive in the VLSI design position, and why are they important?
To excel in VLSI Design, a strong background in electrical engineering, digital and analog design concepts, and semiconductor device fundamentals is required, often supported by a relevant degree. Expertise with industry tools such as Cadence, Synopsys, and Mentor Graphics, as well as knowledge of hardware description languages like Verilog or VHDL, is essential. Attention to detail, strong problem-solving abilities, and effective teamwork and communication skills set top designers apart. These competencies ensure high-quality, innovative chip designs and efficient collaboration in multi-disciplinary engineering environments.
Is VLSI design a good career?
Is Vlsi Design still in demand?
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Cities with the most Vlsi Design job openings:
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The most popular types of Vlsi Design jobs are:
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Full-time
Medical, Dental, Vision, Retirement, PTO
Re-posted 24 days ago
Key responsibilities
Define and enforce synchronization strategies across complex, multi-clock domains in high-speed IPs.
Own the constraint creation process for synthesis and full-chip CDC/RDC methodology to ensure zero-defect silicon.
Collaborate with Architecture and Chip Lead teams to review testability, DFT design, clocking, and reset architectures early in the design cycle.
Broadcom rating
8.7
Based on 23 frontline employees who took The Breakroom Quiz
18th of 161 rated electronics manufacturers
Job description
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Job Description:We are seeking a Senior Digital VLSI Design Engineer with deep expertise in Synthesis, DFT, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) sign-off for high speed complex IPs to be delivered to the SOC teams.
In this role, you will be the technical authority responsible for defining and enforcing synchronization strategies across complex, multi-clock domains in advanced process nodes. You will own the constraint creation process for synthesis, full-chip CDC/RDC methodology, establishing rigorous constraints and waivers to ensure zero-defect silicon. You will collaborate closely with Architecture and Chip Lead teams to review the testability and DFT design, clocking and reset architectures early in the design cycle, identifying potential metastability or reset-glitch issues before RTL freeze.
The ideal candidate has 8+ years of experience and a mastery of structural and functional verification of crossings using industry-standard tools (e.g., SpyGlass CDC/RDC, Spyglass Lint, JasperGold, or Meridian). Experience with high-speed interfaces such as SerDes, LPDDR5/6, DDR4/5 or HBM, where asynchronous boundaries are critical, is highly desired. As a Senior Engineer, you are expected to mentor the broader design team on Synthesis, DFT, CDC/RDC best practices and drive automated flows to streamline sign-off for multi-site global teams.
Requirements:
BSEE required, MSEE/PHD preferred
8+ years of related experience
Compensation and Benefits
The annual base salary range for this position is USD 121,900.00 To USD 195,000.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
About Broadcom
Sourced by ZipRecruiter
Industry
Semiconductor and electronic component manufacturing
Company size
10,000+ Employees
Headquarters location
Palo Alto, CA, US
Year founded
1991