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Vlsi Design Verification Engineer Jobs in Colorado

Broadcom

Design Engineer

Fort Collins, CO

$60K - $96K/yr

Utilize both commercial and in-house EDA tools for design, implementation, and verification ... Solid understanding of VLSI design, CMOS logic, and digital circuit fundamentals. * Familiarity ...

Broadcom, Inc.

Design Engineer

Fort Collins, CO · On-site

$60K - $96K/yr

Utilize both commercial and in-house EDA tools for design, implementation, and verification ... Solid understanding of VLSI design, CMOS logic, and digital circuit fundamentals. * Familiarity ...

Broadcom

Verification Engineer

Fort Collins, CO · On-site

$134K/yr

Collaborate with design, architecture, and verification teams to ensure design quality * Develop ... Bachelor's degree in Electrical/Electronic Engineering, Computer Science * 12+ years of relevant ...

Broadcom

Verification Engineer

Fort Collins, CO · On-site

$134K/yr

Collaborate with design, architecture, and verification teams to ensure design quality * Develop ... Bachelor's degree in Electrical/Electronic Engineering, Computer Science * 8+ years of relevant ...

SOCOMEC

Test Verification Engineer

Longmont, CO · On-site

$80K - $90K/yr

About This Role The Design & Test Verification Engineering / Technologist is a broad ranging position responsible for developing and executing test strategies to verify and validate product designs ...

SOCOMEC

Test Verification Engineer

Boulder, CO · On-site

$80K - $90K/yr

About This Role The Design & Test Verification Engineering / Technologist is a broad ranging position responsible for developing and executing test strategies to verify and validate product designs ...

CesiumAstro

FPGA Verification Engineer II

Westminster, CO · On-site

$113K - $136K/yr

Contribute to the evaluation and technical implementation of FPGA and digital design simulation ... Aid the Lead Verification Engineer in evaluating current processes regarding FPGA and digital ...

CesiumAstro

FPGA Verification Engineer II

Westminster, CO · On-site

$113K - $136K/yr

Contribute to the evaluation and technical implementation of FPGA and digital design simulation ... Aid the Lead Verification Engineer in evaluating current processes regarding FPGA and digital ...

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Showing results 21-40

All JobsVlsi Design Verification Engineer JobsVlsi Design Verification Engineer Jobs in Colorado

Vlsi Design Verification Engineer information

See Colorado salary details

$110.9K

$156.8K

$175.6K

How much do vlsi design verification engineer jobs pay per year?

As of Aug 8, 2026, the average yearly pay for vlsi design verification engineer in Colorado is $156,833.00, according to ZipRecruiter salary data. Most workers in this role earn between $143,000.00 and $174,600.00 per year, depending on experience, location, and employer.

What are some common challenges faced by VLSI design verification engineers during the verification process?

VLSI Design Verification Engineers often encounter challenges such as managing increasingly complex system-on-chip (SoC) designs, ensuring thorough test coverage, and debugging intricate functional issues. Coordinating with cross-functional teams—like design, software, and validation—is essential to align test plans and resolve ambiguities quickly. Additionally, keeping up with evolving verification methodologies and tools (such as UVM or SystemVerilog) requires a commitment to continuous learning, but offers strong career growth opportunities for those who master them.

What are the key skills and qualifications needed to thrive as a VLSI design verification engineer?

To thrive as a VLSI Design Verification Engineer, you need a solid background in digital logic design, computer architecture, and verification methodologies, typically supported by a degree in electrical engineering or a related field. Proficiency with hardware description languages like Verilog or VHDL, simulation tools such as ModelSim or Synopsys VCS, and familiarity with UVM or SystemVerilog are commonly required. Strong analytical thinking, attention to detail, and effective communication are crucial soft skills for identifying design flaws and collaborating with cross-functional teams. These skills and qualifications ensure accurate, reliable chip designs and efficient project execution in the competitive semiconductor industry.

What is the difference between Vlsi Design Verification Engineer vs Vlsi Design Engineer?

AspectVlsi Design Verification EngineerVlsi Design Engineer
Primary FocusVerifying the correctness of VLSI designs through testing and simulationCreating and implementing VLSI chip designs and architectures
Skills & CertificationsHardware description languages (HDL), verification tools, scripting, knowledge of verification methodologiesHDL, digital design, synthesis, timing analysis, and physical design skills
Work EnvironmentDesign teams, verification labs, simulation environmentsDesign teams, synthesis and implementation tools, physical design environments

While both roles require HDL knowledge and work within VLSI teams, the Vlsi Design Verification Engineer primarily focuses on testing and validating designs, whereas the Vlsi Design Engineer is responsible for creating and implementing the actual chip designs.

What is a VLSI design verification engineer?

A VLSI Design Verification Engineer is a specialist responsible for ensuring that integrated circuits (ICs) and systems-on-chip (SoCs) meet their design specifications before manufacturing. They use various verification methodologies, such as simulation, formal verification, and hardware emulation, to identify and fix functional errors in digital designs. Their role is critical in the semiconductor industry to ensure product quality, reduce costly re-spins, and speed up time-to-market. They often work closely with design engineers, using tools like SystemVerilog, UVM, and other verification frameworks.
What are popular job titles related to Vlsi Design Verification Engineer jobs in Colorado? For Vlsi Design Verification Engineer jobs in Colorado, the most frequently searched job titles are:
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Vlsi Design Verification Engineer jobs near you
Infographic showing various Vlsi Design Verification Engineer job openings in Colorado as of August 2026, with employment types broken down into 50% Full Time, and 50% Contract. Highlights an 75% In-person, and 25% Remote job distribution, with an average salary of $156,833 per year, or $75.4 per hour.

Senior Digital VLSI Design Engineer

Broadcom, Inc.

Fort Collins, CO • On-site

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 26 days ago

Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz

19th of 156 rated electronics manufacturers

Job description

Please Note:
1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)
2. If you already have a Candidate Account, please Sign-In before you apply.
Job Description:
We are seeking a Senior Digital VLSI Design Engineer with deep expertise in Synthesis, DFT, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) sign-off for high speed complex IPs to be delivered to the SOC teams.
In this role, you will be the technical authority responsible for defining and enforcing synchronization strategies across complex, multi-clock domains in advanced process nodes. You will own the constraint creation process for synthesis, full-chip CDC/RDC methodology, establishing rigorous constraints and waivers to ensure zero-defect silicon. You will collaborate closely with Architecture and Chip Lead teams to review the testability and DFT design, clocking and reset architectures early in the design cycle, identifying potential metastability or reset-glitch issues before RTL freeze.
The ideal candidate has 8+ years of experience and a mastery of structural and functional verification of crossings using industry-standard tools (e.g., SpyGlass CDC/RDC, Spyglass Lint, JasperGold, or Meridian). Experience with high-speed interfaces such as SerDes, LPDDR5/6, DDR4/5 or HBM, where asynchronous boundaries are critical, is highly desired. As a Senior Engineer, you are expected to mentor the broader design team on Synthesis, DFT, CDC/RDC best practices and drive automated flows to streamline sign-off for multi-site global teams.
Requirements:
  • BSEE required, MSEE/PHD preferred
  • 8+ years of related experience

Compensation and Benefits
The annual base salary range for this position is USD 121,900.00 To USD 195,000.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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