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Ai Chip Design Rtl Jobs in Colorado (NOW HIRING)

Broadcom, Inc.

RTL Design Sign Off Lead

Fort Collins, CO · On-site

$108K - $172.80K/yr

You will collaborate closely with Architecture and Chip Lead teams to review the testability and DFT design, clocking and reset architectures early in the design cycle, identifying potential ...

Broadcom

RTL Design Sign Off Lead

Fort Collins, CO

$108K - $172.80K/yr

You will collaborate closely with Architecture and Chip Lead teams to review the testability and DFT design, clocking and reset architectures early in the design cycle, identifying potential ...

Broadcom

Verification Engineer

Fort Collins, CO

$120K - $192K/yr

Leverage AI-assisted tools (e.g., ChatGPT, Gemini, Cursor) to enhance productivity Required ... Understanding of chip design flows and tools * Knowledge of CPU, DDR, bus, network protocols, or ...

Intel

SoC Logic Design Engineer

Fort Collins, CO · On-site

$141.91K - $269.10K/yr

Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design ... chip SoC or discrete component design. Participates in the definition of architecture and ...

Broadcom, Inc.

IP Integration Engineer

Fort Collins, CO · On-site

$91K - $146K/yr

... AI engines, supercomputers, networking, to low power and most advanced wireless solutions, as some ... Have an understanding of the ASIC design flow including FET design, RTL, synthesis, timing ...

Broadcom

IP Integration Engineer

Fort Collins, CO

$91K - $146K/yr

... AI engines, supercomputers, networking, to low power and most advanced wireless solutions, as some ... Have an understanding of the ASIC design flow including FET design, RTL, synthesis, timing ...

Broadcom

Package Design Engineer

Fort Collins, CO

$141.30K - $226K/yr

Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages ... AI), networking, high-performance computing (HPC), and 5G base stations. These designs include ...

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Ai Chip Design Rtl information

What are the key skills and qualifications needed to thrive as an AI Chip Design RTL Engineer, and why are they important?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.

What are some common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What are AI Chip Design RTL engineers?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

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Ai Chip Design Rtl jobs near you
Design Engineer - Chip Floorplanner

Design Engineer - Chip Floorplanner

Broadcom, Inc.

Fort Collins, CO • On-site

$127.10K - $203.40K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 16 days ago

Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz

12th of 137 rated electronics manufacturers

Job description

Please Note:
1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)
2. If you already have a Candidate Account, please Sign-In before you apply.
Job Description:
Be part of the Custom Silicon Design Team within Broadcom's ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular, Networking, Computing, and Storage products. This position offers the opportunity to work on high-performance SoC designs operating at speeds exceeding 1 GHz, from concept through production.
Role Overview
This Floorplanning Engineer role focuses on chip-level physical architecture and integration for advanced ASICs in deep sub-micron technologies. The position provides hands-on experience with the latest 3 nm and smaller process nodes, defining and optimizing the overall die layout, including partitioning, hierarchy, and placement of major functional blocks, memories, and I/O structures for AI, computing, and networking SoCs.
Key Responsibilities
  • Define and optimize top-level floorplan architecture, including die size estimation, hierarchy definition, and partitioning.
  • Drive macro placement, power grid design, clock distribution planning, pin placement, and feedthrough optimization.
  • Collaborate closely with RTL, timing, and packaging teams to balance performance, power, and area (PPA) targets.
  • Lead top-level timing closure, congestion analysis, and ECO implementation to ensure clean tapeout readiness.
  • Coordinate with block owners and integration teams for smooth block-level to top-level convergence.
  • Support cross-functional design integration, providing guidance and technical support to internal and external partners.
  • Apply a deep understanding of block PnR, timing closure, physical verification, and IR/EM analysis to achieve signoff-quality results.
  • Contribute to design flow automation and methodology development for advanced process technologies.

Technical Skills / Background
  • Strong foundation in VLSI design principles and ASIC physical design fundamentals.
  • In-depth experience with floorplanning, die partitioning, and hierarchical design.
  • Working knowledge of PLLs, clock networks, power delivery, and timing-critical structures.
  • Familiarity with physical verification, DRC/LVS, and congestion/power analysis.
  • Proven ability to drive PPA optimization through innovative layout and planning strategies.

Coding & Tool Proficiency
  • Strong experience with TCL scripting and Linux environments is required.
  • Proficiency in Python, Perl, or Ruby is preferred.
  • Experience with Cadence or equivalent physical design tools is highly desirable.

Collaboration and Leadership
  • Excellent communication, organizational, and problem-solving skills.
  • Ability to work effectively with customers and cross-functional teams across global sites and time zones.
  • Skilled at organizing and presenting large data sets, managing multiple priorities efficiently.
  • Exercises independent judgment and strong engineering insight in defining methods, techniques, and evaluation criteria.
  • Provides technical leadership, mentors others, and leads execution of new initiatives.

Education and Experience
  • BS in Electrical or Computer Engineering with 12+ years of relevant experience, or
  • MS in Electrical or Computer Engineering with 10+ years of relevant experience.

Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $127,100 - $203,400.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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